AT&T 3B2/300 Technical Reference Manual page 316

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MAU Coprocessor Mode.
In the Coprocessor Mode, the system board CPU initiates a MAU
transaction by doing a coprocessor broadcast access. This sends a 32-bit word to the MAU Command
Register. The MAU checks the Identification (ID) field of the Command Register against the MAU
ID (0). If an ID matches the stored ID, the 32-bit word is stored in the Command Register.
If any Operand Specifier in the command word indicates that an operand is to be obtained from
main memory, the MAU waits until the proper number of coprocessor data fetch bus transactions occur.
The MAU does the operation specified and generates a result, condition codes, and possibly an
exception. The MAU asserts a DONE signal and waits for the coprocessor (system board CPU) status
fetch. If an exception is present, the MAU faults the access and goes to an idle state. If there is no
exception, a word containing the current Auxiliary Status Register (ASR) is returned in response to the
status fetch.
If the results are to be written to main memory, The MAU waits until the proper number of
coprocessor data write bus transactions occur to transfer the results and then goes to an idle state.
Address Decoder
The address decoder translates physical CPU /MMU addresses into chip selects (enables) for the
various memory and peripheral circuits on the system board and feature cards. The address decoder is
built from Programmable Logic Arrays (PLAs) and four 3 /8 decoders. The chip select signals are also
used to generate Wait Select (WSEL) signals appropriate for the access time of each synchronous device.
For devices on the system board, a fixed number of wait states are generated by the address decoder.
The chip selects and controls decoded from physical address bits 26-12, Physical Address Strobe
(PAS[O]), Interrupt Acknowledge (IACK[O]) are summarized in Figure 3-21.
FUNCTIONAL DESCRIPTION 3-63