AT&T 3B2/300 Technical Reference Manual page 321

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
VERSION 2-SYSTEM BOARD CONTROL AND ST A TUS REGISTER BIT ASSIGNMENTS
WRITE
BIT
DESCRIPTION
ADDRESS
FUNCTION CONTROL
15 ERROR TIMER TIMEOUT Ox 00044000 CLEAR HS
14 MEMORY PARITY ERROR Ox 00044004 CLEAR HS
13 SYSTEM RESET REQUEST Ox 00044008 SET CR
12 ALIGNMENT FAULT Ox 0004400C CLEAR HS
11 DIAGNOSTIC INDICATOR ON
Ox 00044010
SET
Ox 00044014 CLEAR
10
FLOPPY MOTOR ON Ox 00044018 SET
Ox 0004401C CLEAR
09 RESERVED
08
INHIBIT TIMERS Ox 00044020 SET
Ox 00044024 CLEAR
07 INHIBIT FAULTS Ox 00044028 SET
Ox 0004402C CLEAR
06 PERIODIC INTERRUPT Ox 00042010 CLEAR HS
05 PIR (LEVEL 8 INTERRUPT) Ox 00044038 SET
Ox 0004403C CLEAR
04
PIR (LEVEL 9 INTERRUPT) Ox 00044030 SET
Ox 00044034 CLEAR
03 UART INTERRUPT
-
-
BO
02
FLOPPY DISK INTERRUPT - - BO
01 OMA INTERRUPT - - BO
00 INPUT/OUTPUT BOARD FAIL - - BO
LEGEND:
BO
CR
DMA
HS
PC
PIR
PS
SR
Signal originates elsewhere and is only buffered in the CSR
Cleared by "system reset" signal
Direct Memory Access
Set by hardware
Cleared by programmed control
Programmed Interrupt Request
Set by programmed control
Set by "system reset" signal
Figure 3-22: Version 2 System Board CSR Bit Assignments
3-68 TECHNICAL REFERENCE MANUAL
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PS
PS
PS
PS
PS
PS
PS
PS
PS
PS
PS
PS
PS
SR
SR
SR
SR