AT&T 3B2/300 Technical Reference Manual page 270

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System Board Peripheral Controller Read Operation.
Figure 3-6 shows the system board
peripheral controller read operation. A system board CPU read operation of a peripheral controller
(feature card) starts with the Peripheral Read/Write signal (PRl WO) (Read=l), Peripheral Physical
Address signals (PPA23-00[l ]), and the Peripheral Card (Chip) Select signal (PCS) occurring
simultaneously. The selected feature card sends the PSIZE16[0] signal to define its data width (8
bits=l, 16 bits=O) in response to the PCS[O] signal. The system board CPU sends the Physical Address
Strobe (PPAS[O]) to the feature card when the address lines (PP A23-00[l]) are stable. The Peripheral
Data Strobes (PDSOl-00[0]) are sent to the feature card to select the data byte(s) to be returned during
the data bus transaction. The feature card sends the data via the Peripheral Data bus (PDlS-00[1] for
16-bit peripherals or PD07-00[1] for 8-bit peripherals) and sends the Peripheral Data Transfer
Acknowledge (PDTACK[O]) signal after a minimum data setup time. The system board relinquishes the
bus by driving the address and data strobes inactive (high=l) and then tri-stating all of its 1/0 bus
signals. The feature card relinquishes the bus when it sees the inactive address and data strobes.
FUNCTIONAL DESCRIPTION 3-17