AT&T 3B2/300 Technical Reference Manual page 341

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
VERSION 3 382 COMPUTER SYSTEM BOARD
CLOCKS:
- 24 MHz
- 22 MHz
- 18 MHz
-16MHz
- 5
MHz
CENTRAL
PROCESSING
UNIT, MEMORY
MANAGEMENT
UNIT(S) AND
MATH
ACCELERATION
UNIT
r----,
I 0 OR 1 I
I
UBus
I
I
SLOT
I
I I
I I
I I
I I
I I
L-- _.J
CA[31-00]1,
CD[31-00]1
PBus
BUFFERS
WAIT STATE
AND STROBE
GENERATOR
SLAVE BUS
BUFFERS
BuBus
BUFFERS
INTERRUPT
CONTROL,
TIMERS,
EPROMs CONTROL AND
TOD, NVRAM,
FAULT LATCHES
(2 OR 4)
STATUS REGISTER
SADD[31-00]1, SD[31-00]1
BYPASS REQUEST
AND
CONTROL SEQUENCERS
ADDRESS
DECODER/
CHIP SELECT
GENERATION
MICROBUS
ARBITER,
PBus REQUEST
GENERATION
r---------,
I 1, 2, 3 I
BA[27-00]l, BD[31-00]l I
OR
4 I
,------.... -------------------.;.'-1
I
I BuBus I
r--------,
I O OR 3 I
I
PBUS ....._ _ _ ,.
I SLOTS
I I
L--------.J
MEMORY
AND REFRESH
SEQUENCERS
MEMORY
BUS BUFFERS
MEMORY
CONTROLLER
w/ECC
MUXA[l0-00]1,
MD[31-00]1,
MCB[ll-00]1
3B2 1/0 BUS
ADAPTER
PPA[l6-0l]l,
PD[lS-00]1
IPA[07-00]1,
IPD[07-00]1
OMA
SUBSYSTEM
BUFFERS
---, r------- ---------,
- - ~ - - , I I
I I I
I I I
I I I
2 OR 4
: : 7 OR 12 3B2 1/0 SLOTS :
MEMORY I I I
I SLOTS I
L - - - - - - - - - - - - - - - - - .J
L------.J
Figure 3-27: Version 3 3B2 Computer System
Board - Functional Block Diagram
3-88 TECHNICAL REFERENCE MANUAL
I
SLOTS
I
I I
L---------.J
FLOPPY DISK
CONTROLLER
DIRECT MEMORY
ACCESS
CONTROLLER,
PAGE REGISTERS
DUAL UNIVERSAL
ASYNCHRONOUS
RECEIVER/
TRANSMITTER
CONSOLE
AND CONTTY