AT&T 3B2/300 Technical Reference Manual page 278

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Bus Arbitration
The main memory has two ports on the system board. One port is reserved for the system board
(main) CPU. The other port is for the
1/0
bus. Access to the main memory is controlled by arbitration
logic on the system board. This logic also handles the periodic refresh of the Dynamic Random Access
Memory (DRAM). The arbitration logic prioritizes bus requests depending on the request source. The
bus arbitration priorities are listed below:
• Memory refresh operation (highest priority)
• CPU to main memory interlock requests
• Integral floppy to main memory requests
• CPU to buffered microbus requests (includes CPU to memory)
• Buffered microbus to memory requests and feature card to memory requests (equal, rotating
priority).
Any feature card can be the
J/0
bus master. Feature cards can only request access to the
1/0
bus
for reading or writing main memory. A feature card requests other types of service (other than bus
resources) from the system board CPU via an interrupt request. A typical scenario of how the feature
card gains
1/0
bus access is as follows:
A feature card requests
1/0
bus access by asserting the Peripheral Bus Request (PBRQ[O]) signal.
The PBRQ signal can only be asserted by a feature card if PBRQ is first inactive for a minimum of
80 nanoseconds. This delay provides a window sufficient for all feature cards to detect an inactive
PBRQ. Similarly, the arbiter delays the assertion of the Peripheral Bus Acknowledge (PBACK[O])
signal for approximately 200 nanoseconds to provide enough time for all interested feature cards to
request bus access and inhibit the Peripheral Bus Acknowledge (PBACK[O]) signal propagation.
The PBACK[O] is daisy-chained through all feature cards. PBACKI[O] refers to the input
acknowledge signal to a feature card. PBACKO[O] refers to the output acknowledge signal from a
feature card. A feature card requesting bus access has 200 nanoseconds to block the PBACKI[O]
from propagating to PBACKO[O] if the feature card wants to access the 1/0 bus. The feature card
also asserts the Peripheral Bus Busy (PBUSY[O]) for the duration of the bus cycle. The PBACK
signal is negated when the system board detects the PBUSY. The PBUSY signal notifies other
feature cards that the
1/0
bus is in use.
When multiple feature cards request
1/0
bus access, the feature card physically closest to the
system board has the first access. The feature card bus access priority is determined by the feature card
location on the bus. Feature card slot 1 has the first access; feature card slot 12 has the last access. Bus
access is shared in this sequence. Once a feature card slot has accessed the bus, it cannot regain bus
access until all other slots requesting service have been accessed in sequence from 1 through 12.
For Version 3 computers, the buffered microbus slots have equal, rotating priority with the
1/0
bus
slots. That is, if buffered microbus slot O has the bus now, 1/0 bus would have it next, followed by
buffered microbus slot 1, 1/0 bus, buffered microbus slot 2, etc.
Multiple Input/Output Bus Accesses
More than one data transfer (bus access) can be done by the same feature card in one bus cycle.
Multiple bus accesses are done without the need for additional bus arbitration. This feature is only
applicable to feature cards; the system board cannot do multiple accesses on the
1/0
bus.
The Peripheral Bus Busy (PBUSY[O]) signal asserted by the feature card enables the feature card to
maintain control of the
J/0
bus. The feature card can perform a maximum of four transfers without
negating the PBUSY signal.
FUNCTIONAL DESCRIPTION 3-25