AT&T 3B2/300 Technical Reference Manual page 471

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
XDC CARD ADDRESS MAP
MEMORY
1/0
CHIP
DESCRIPTION
ADDRESS ADDRESS SELECT
ACCESS
Ox 00000 - LCS DRAM (VECTOR TABLE) READ/WRITE
Ox 00080 -
LCS DRAM (APPLJCA TION) READ/WRITE
Ox 20000 - LCS NOT USED -
Ox 40000
- - NOT USED -
Ox 80000
-
MCS SBD DPDRAM READ/WRITE
Ox AOOOO
- MCS NOT USED -
Ox COOOO Ox 0400 PSO
NOT USED
-
Ox C0080 Ox 0480 PSO ID /VECTOR REGISTER WRITE
Ox C0082 Ox 0482 PSI
PAGE REGISTER
WRITE
Ox C0084 Ox 0484 PSI PCSR BITS 7-0 READ
Ox C0086 Ox 0486 PSI
RESERVED
Ox C0088 Ox 0488 PSI
PCSR BIT O (INTO)
(NOTE 1)
Ox C0089
Ox 0489 PSI PCSR BIT 1 (INTI) (NOTE 1)
Ox COOSA Ox 048A PSI PCSR BIT 2 (INT2) (NOTE 1)
Ox C008B
Ox 048B PSI PCSR BIT 3 (INT3) (NOTE 1)
Ox C008C Ox 048C PSI PCSR BIT 4 (RESET PCSR4) (NOTE 2)
Ox C008D
Ox 048D PSI PCSR BIT 5 (ARDY) READ/WRITE
Ox C008E Ox 048E PSI
PCSR BIT 6 (SET PCSR4) (NOTE 2)
Ox C008F Ox 048F PSI PCSR BIT 7 (PINTl[O]) (NOTE 1)
Ox C0090 Ox 0490 PSI NOT USED
-
Ox COlOO Ox 0500 PS2 NOT USED
-
Ox C0180 Ox 0580
PS3 NOT USED -
Ox C0200 Ox 0600 PS4 HOC CHIP FIFO READ/WRITE
Ox C0202 Ox 0602 PS4
HOC COMMAND REGISTER WRITE
Ox C0202 Ox 0602 PS4 HOC ST A TUS REGISTER READ
Ox C0204 Ox 0604 PS4
NOT USED
-
Ox C0280 Ox 0680 PSS
NOT USED
-
Ox C0300
Ox 0700 PS6 NOT USED -
Ox C0400 Ox FFOO 80186
80186 CONTROL BLOCK -
Ox C0420
Ox FF20 80186 INTERRUPT CONTROL -
Ox C0450 Ox FFSO 80186
TIMER O CONTROL -
Ox C0458
Ox FF58 80186 TIMER 1 CONTROL -
Ox C0460 Ox FF60
80186 TIMER 2 CONTROL -
Ox C0466 Ox FF66 80186 NOT USED
-
Ox C04AO Ox FFAO 80186
CHIP SELECT CONTROL -
Ox C04AA Ox FFAA 80186 NOT USED -
Ox C04CO Ox FFCO 80186
OMA O CONTROL -
Ox C04CC
Ox FFCC 80186 NOT USED
-
Ox C04DO Ox FFDO 80186
OMA 1 CONTROL -
Ox C04DC Ox FFDC 80186 NOT USED -
Ox C04FE Ox FFFE 80186
RELOCATION REGISTER
Ox COSOO - 80186
NOT USED -
Ox FCOOO -
ucs
ROM READ
NOTES:
1. Bit is cleared (reset) by 80186 Microprocessor access.
2. PCSR6 is set [l] by 80186 Microprocessor access to reset the hard disk controller.
PCSR4 is set [l] by either system reset or by addressing PCSR6.
PCSR4 (HOC reset) is turned off [OJ by addressing PCSR4.
LEGEND:
ARDY
OMA
DPDRAM
DRAM
HOC
LCS
MCS
PCSR
PS
SBD
ucs
Asynchronous Data Ready
Direct Memory Access
Dual Port Dynamic Random Access Memory
Dynamic Random Access Memory
Hard Disk Controller
Lower RAM Chip Select
Memory Chip Select
Peripheral Control and Status Register
Peripheral Select
System Board
Upper RAM Chip Select
Figure 3-68: CM195K XDC Card Address Map
3-218 TECHNICAL REFERENCE MANUAL
WIDTH SIZE
(BITS) (BYTES)
16 128
16
127.9K
- 128K
-
256K
16 128K/PAGE
-
128K
- 128
16 2
7
8 1
1
1
1
1
1
1
1
1
16
111
-
128
- 128
8 1
8 1
8 1
16 126
16
128
16 128
16
256
16 32
16
8
16
8
16 6
-
58
16 10
- 22
16 12
-
4
16 12
- 34
16 2
- 47872
16 16K