AT&T 3B2/300 Technical Reference Manual page 360

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Math Acceleration Unit
The WE 32106 Math Acceleration Unit (MAU) is used on the CM518A System Board.
Note: The WE 32100 chipset is covered in the "CM190A/ED-4C637-30 System Board"
section for Version 2 system boards. Refer to that section for detailed information on
the CPU/MMU/MAU chips of the CM518A System Board.
The CM518B/C System Boards use the WE 32206 MAU. The MAU is used in a coprocessor mode
to provide hardware floating point capability for the WE 32200 Microprocessor. The MAU peripheral
mode is not used in this application; the MAU chip select is held to a logic 1 through a pull up resistor
to VCC. The MAU provides single (32-bit), double (64-bit), and double-extended (80-bit) precision.
The single precision format provides an 8-bit exponent and an exponent bias allowing the reciprocal of
all normalized numbers to be represented without overflow. Double precision provides an exponent
range sufficient for the product of eight 32-bit terms without overflow. Double-extended precision
provides a format with a range and precision that is greater than double precision. Double-extended
precision numbers lessen the chance of a result being contaminated by excessive roundoff error.
The MAU supports add, subtract, multiply, divide, remainder, square root, and compare operations.
The operand, result, status, and command information transfers take place over a 32-bit, bidirectional
data bus with the WE 32200 Microprocessor. Figure 3-32 is a functional block diagram of the
WE 32206 MAU. The WE 32206 is a 125-pin ceramic pin-array package using CMOS technology and
operating at 24 MHz.
MAU Registers.
The MAU contains four register types:
• Auxiliary Status Register
• Operand Registers
• Command Register
• Data Register.
These registers provide status, command, and control for the MAU.
FUNCTIONAL DESCRIPTION 3-107