AT&T 3B2/300 Technical Reference Manual page 398

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Memory Control Signals
The memory control signals include the following:
BANKENO[O]
The "bank enable O" signal is used to select (enable) the read or write access of
memory array bank 0.
BANKENl[O]
The "bank enable 1" signal is used to select (enable) the read or write access of
memory array bank 1.
CAS3-0[0] The "column address strobes" signal is used to strobe (enable) the column address.
WE[O] The "write enable" signal is used to write data to the memory.
RAS[O]
The "row address strobe" signal is used to strobe (enable) the row address.
Memory Address Signals
Memory address signals are supplied from the Address Generation logic of the Dual Port Dynamic
Random Access Memory Controller via a 10-bit multiplexed memory address bus. Control signals
applied to the memory cards determine whether the address is used as a row or column address. The
relationship between the
1/0
bus and the multiplexed memory address bus for row and column
addresses is shown in the following table. Note that all multiplexed address bus bits are NOT used by
a given RAM card.
INPUT /OUTPUT MULTIPLEXED MEMORY
ADDRESS BUS MEMORY CARD TYPE
ADDRESS
ROW COLUMN
BUS
ADDRESS ADDRESS
BITS
CM191A
CM191B/C/D
CM192B
BITS BITS
02 19 9
NC
X X
10 18 8
NC
X X
09 17 7
X X
X
08 16 6
X X
X
07 15
5
X X X
06 14 4
X X X
05
13
3
X X X
04 12 2
X X X
03 11 1
X X X
02 10 0
X
NC NC
Data and Parity Signals
The data bus includes 32 data bits (MD31-00[l]) and 4 bits of byte parity (MP AR3-0[1 ]). The
relationship of the parity bits to the data bytes is shown in the following table.
MPARO MPARl MPAR2
MPAR3
MD31- 24 MD23 - 16 MD15 - 08 MD07- 00
FUNCTIONAL DESCRIPTION 3-145