AT&T 3B2/300 Technical Reference Manual page 315

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
Data Register
The system board CPU (WE 32100) uses the MAU as a coprocessor; the peripheral mode of the
MAU is NOT used in this application. The Data Register (DR) is used to read and write operands
(registers F3-FO) in the peripheral mode. The DR is an 82-bit register. The DR is addressed in the
peripheral mode as three 32-bit registers. When exceptions occur in either the coprocessor or peripheral
modes, the DR stores the data supplied by the trap handler. This exception data is read when an
Extract Result on Fault (EROF) instruction (opcode) is executed. The format of the exception data stored
in the DR by the trap handler is as follows.
INV AUD OPERATION
If either of the source operands is a trapping Not a Number (NAN), then DR stores
the NAN converted to double-extended precision (80 bits) if necessary. If both
source operands are trapping NANs or infinities of different signs, then the second
operand (OP2) is stored in the DR in double precision (80 bits).
OVERFLOW or UNDERFLOW
The significant (fraction) along with the 17-bit internal result exponent and the
result sign are stored in the DR. The most significant bit of the 17-bit exponent is
like a sign bit in 2's complement notation. An addition bit (bit 79) in the exponent
ensures that no significant exponent bits are lost from an internal representation
when an overflow or underflow condition occurs. The exponent is biased by
16,383. The format of the data in the DR for an overflow or underflow exception is
as follows.
BITS
81
80 - 64
63 62 - 00
FIELD SIGN EXPONENT J FRACTION
DIVIDE BY ZERO
INEXACT
The dividend (OP2) converted to double-extended precision, if necessary, is stored
in the DR for a divide by zero exception.
The rounded result converted to double-extended precision, if necessary, is stored in
the DR for and inexact exception.
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