AT&T 3B2/300 Technical Reference Manual page 296

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Memory Management Unit
The Memory Management Unit (MMU) on System Board, ED-4C637-30 is a WE 32101 Memory
Management Unit. The MMU on a CM190A System Board is part of the WE 32002 CPU Module.
Figure 3-15 shows how the MMU connects to the system. Figure 3-16 is a block diagram of the MMU.
The internal MMU address spectrum is shown in Figure 3-17. Figure 3-18 shows virtual to physical
address translation for contiguous memory segments. Figure 3-19 shows virtual to physical address
translation for paged segments.
The MMU manipulates the microprocessor's address space by translating the virtual microprocessor
addresses into physical address information. The 32-bit address can access over 4 gigabytes (2
32 )
of
system memory or peripherals. The MMU also supports demand paged and demand segmented virtual
memory. This permits large programs to efficiently use physical memory space.
The MMU divides the virtual address space into four sections. Each of these four sections can be
subdivided into as many as 8K segments per section. These segments can be either contiguous or
paged and are mapped into the physical address space by the MMU. A contiguous segment can be as
large as 128K bytes. A paged segment can contain up to sixty-four 2K byte pages. Contiguous and
paged segments start at an address in physical memory that is a multiple of 32 bytes.
Virtual addresses are relative addresses of an active process. Physical addresses are addresses that
the main store controller can interpret as the true physical location of the memory. The function of the
MMU is to translate virtual addresses to physical addresses. The address of each byte within a 2K byte
block (offset) is not translated because the smallest size data block that can be placed in the main store
by the MMU is 2K bytes. Therefore, the lower 11 bits of the virtual address spectrum and the
lower 11 bits of the physical address spectrum are the same. The MMU stores information describing
the physical location of blocks of 2K bytes of process data. This information is called descriptors. The
descriptors are stored in the MMU descriptor caches. The MMU uses two descriptor caches: Segment
Descriptor Cache (SDC) and Page Descriptor Cache (PDC).
Virtual address space is further described in Appendix A.
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