AT&T 3B2/300 Technical Reference Manual page 479

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
ISC CARD ADDRESS MAP
MEMORY
1/0
CHIP
ADDRESS ADDRESS SELECT
DESCRIPTION
Ox 00000
-
LCS
RAM (VECTOR TABLE)
Ox 00080
-
LCS RAM (DEMON)
Ox 00180 - LCS RAM (USER)
Ox 20000 - LCS NOT USED
Ox 40000 - - NOT USED
Ox 60000
-
- RAM REFRESH
Ox 80000 - MCS DPDRAM
Ox AOOOO - MCS NOT USED
Ox COOOO Ox 0400 PSO
DEMON
Ox C0080
Ox 0480 PSO ID/VECTOR REGISTER
Ox C0082 Ox 0482 PSI PAGE REGISTER
Ox C0084 Ox 0484 PSI PCSR BITS 7-0
Ox C0086
Ox 0486 PSI RESERVED
Ox C0088
Ox 0488 PSI PCSR BIT O (INTO)
Ox C0089 Ox 0489 PSI PCSR BIT 1 (INTI)
Ox COOSA Ox 048A PSI PCSR BIT 2 (INT2)
Ox C008B Ox 0488 PSI PCSR BIT 3 (INT3)
Ox C008C
Ox 048C PSI PCSR BIT 4 (NOT USED)
Ox C008D Ox 048D PSI PCSR BIT 5 (NOT USED)
Ox C008E Ox 048E PSI
PCSR BIT 6 (BAF)
Ox C008F
Ox 048F PSI PCSR BIT 7 (PINT)
Ox COlOO
Ox 0500 PS2 8237 OMA CONTROLLER (NOTE 3)
I ' I I
'
Ox COllF Ox 051F PS2 8237 DMA CONTROLLER
Ox C0180
Ox 0580 PS3 8274 CHANNEL A DATA
Ox C0182 Ox 0582 PS3 8274 CHANNEL B DATA
Ox C0184 Ox 0584 PS3
8274 CHANNEL A CONTROL
Ox C0186
Ox 0586 PS3 8274 CHANNEL B CONTROL
Ox C0200 Ox 0600 PS4 NRZI CHANNEL A OFF
Ox C0202 Ox 0602 PS4 NRZI CHANNEL A ON
Ox C0204 Ox 0604 PS4
NRZI CHANNEL B OFF
Ox C0206 Ox 0606 PS4 NRZI CHANNEL B ON
Ox C0280 Ox 0680 PSS SANITY FLIP-FLOP RESET
Ox C0300 Ox 0700
PS6 RESERVED
Ox C0400 Ox FFOO 80186 80186 CONTROL BLOCK
Ox C0420 Ox FF20 80186
INTERRUPT CONTROL
Ox C0450 Ox FFSO
80186 TIMER O CONTROL
Ox C045B Ox FFSB
80186 TIMER 1 CONTROL
Ox C0460 Ox FF60 80186 TIMER 2 CONTROL
Ox C04AO Ox FFAO 80186
CHIP SELECT CONTROL
Ox C04CO Ox FFCO 80186 OMA O CONTROL
Ox C04FD Ox FFDO 80186
OMA 1 CONTROL
Ox C04FE
Ox FFFE 80186 RELOCATION REGISTER
Ox F8000
-
ucs
ROM
NOTES:
1.
Bit is cleared by 80186 Microprocessor access.
2. Bit is set to O by 80186 Microprocessor access
unless a "dummy" read is pending.
3. Only even addresses are used in this range.
4. Timer 2 and DMA channel 1 provide RAM refresh for !SC.
LEGEND:
BAF
DMA
DPDRAM
LCS
MCS
NRZI
PCSR
PS
ucs
Bus Abort Feature
Direct Memory Access
Dual Port Dynamic Random Access Memory
Lower RAM Chip Select
Memory Chip Select
Nonretum to Zero Insertion
Peripheral Control and Status Register
Peripheral Chip Select
Upper RAM Chip Select
Figure 3-70: CM195T ISC Card Address Map
3-226 TECHNICAL REFERENCE MANUAL
WIDTH SIZE
ACCESS
(BITS) (BYTES)
READ/WRITE 16 128
READ/WRITE 16 256
READ/WRITE 16 127.6K
- - 128K
- - 128K
READ/WRITE 16 128K
READ/WRITE 16 128K
- - 128K
- -
-
WRITE 16
WRITE 7
READ 8
(NOTE 1) 1
(NOTE 1) 1
(NOTE 1) 1
(NOTE 1) 1
1
1
(NOTE 2) 1
(NOTE 1) 1
READ/WRITE 8
' I
'
READ/WRITE 8
READ/WRITE
12/8
READ/WRITE 12/8
READ/WRITE
12/8
READ/WRITE
12/8
READ/WRITE 16
READ/WRITE 16
READ/WRITE 16
READ/WRITE 16
READ/WRITE 16
16
16
16
16
(NOTE 4) 16
16
16
(NOTE 4) 16
- 16
READ/WRITE 16 32K