AT&T 3B2/300 Technical Reference Manual page 347

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
R-1 Bits 08 and 07 are the Register-Initial Context (R-I) bits. These bits control the CPU
context switching strategy. The I bit (bit 07) determines if a process executes from
initial (I=l) or intermediate saved context (I=O). The R bit (bit 08, read only)
determines if the registers of a process should be saved during a process switch
(R=l).
ISC
Bits 06-03 are the Internal State Code (ISC) bits. The ISC bits are used to
distinguish between exceptions of the same type. This field is used with the
Exception Type (ET) field to determine when exception occurred. Traps, exceptions,
and faults are equivalent with respect to ISC. Normal exceptions are decoded on a
priority scheme if more than one occurs in a particular cycle. Exceptional
conditions that reset the PSW flags are indicated by an asterisk (*) in the following
data.
EXCEPTION ISC BITS
TYPE
EXCEPTION
6543
NORMAL INTEGER ZERO-DIVIDE 0 0 0 0*
EXCEPTION TRACE TRAP
0 0 0 1
(ET=ll) ILLEGAL OPCODE 0 0 1 0
RESERVED OPCODE 0 0 1 1
INV AUD DESCRIPTOR
0 1 0 0*
EXTERNAL MEMORY FAULT 0 1 0 1
GATE VECTOR FAULT 0 1 1 0
ILLEGAL LEVEL CHANGE 0 1 1 1
RESERVED DATA TYPE 1 0 0 0*
INTEGER OVERFLOW 1 0 0 1
PRIVILEGED OPCODE 1 0 1 0
BREAKPOINT TRAP 1 0 1 1
PRIVILEGED REGISTER 1 1 1 1
STACK STACK BOUND 0000
EXCEPTION STACK FAULT 0 0 0 1
(ET=lO) INTERRUPT ID FETCH 0 0 1 0
PROCESS OLD PCB FAULT
0000
EXCEPTION GATE PCB FAULT
0 0 0 1
(ET=Ol) NEW PCB FAULT 0 1 0 0
RESET
OLD PCB FAULT 0000
EXCEPTION SYSTEM DATA 0 0 0 1
(ET=OO) INTERRUPT STACK FAULT 0 0 1 0
EXTERNAL RESET 0 0 1 1
NEW PCB FAULT 0 1 0 0
GATE VECTOR FAULT 0 1 1 0
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