AT&T 3B2/300 Technical Reference Manual page 380

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Dynamic Random Access Memory Controller
General.
The system main memory is Dynamic Random Access Memory (DRAM). The DRAM
Controller provides the system board CPU direct access to the 1/0 bus without passing through the
RAM. The DRAM Controller handles the exchange of data and address information between the 1/0
bus and the system board CPU when operating in the "bypass mode."
Figure 3-36 is a functional block diagram of the DRAM Controller. The DRAM Controller for RAM
is divided into the following functional areas:
• Address Generation Logic (address multiplexer)
• Request Generator
• Arbitration Logic
• Memory Refresh Logic
• Sequencer
• Bypass Logic
• Data Byte Rotate Unit Logic
• Parity Generation and Checking Logic.
Each of these functional areas is briefly described in the following paragraphs.
FUNCTIONAL DESCRIPTION 3-127