AT&T 3B2/300 Technical Reference Manual page 268

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Address Bus Signals-PPA23-00[l).
The 24 bidirectional (tri-state) address leads provide a
maximum direct address capability of 16 megabytes.
Note: For Version 2 computers, the two-most significant address bus bits (bits 23 and 22) are
reserved and must always be equal to logical signal zero by all peripherals. Therefore,
the actual peripheral address capability used is 4 megabytes.
Data Bus Signals-PD15-00[1). The 16 bidirectional (tri-state) data leads provide for byte or
half-word data transfer.
Control Bus Signals.
The Control Bus signals include status, strobes, feature card select, interrupts,
error detection, and reset signals. The status signals identify the type of bus cycle (read or write) and
the word width (8 or 16 bits) of a feature card. Strobes are used to control the transfer of data.
PBUSY[O) The Peripheral Bus Busy (PBUSY) signal is asserted by a feature card after receipt of
a bus acknowledge (PBACKIO). PBUSY is asserted during the entire bus cycle to
notify all other feature cards that the I/0 bus is being used. PBUSY allows
multiple accesses by the same bus master without relinquishing control of the bus
between data transfers. The maximum of four transfers in one 8 microseconds I/0
bus cycle is allowed.
PCS12-0l[OJ
The Peripheral Card (Chip) Select (PCS) signals are asserted by the system board to
enable (select) the feature cards. For the 3B2/400, 600, 700, and 1000 computers,
12 peripheral chip selects (PCS12-01) are used. For the 3B2/500 computer, 7
peripheral chip selects (PCS07-01) are used. For the 3B2/300 and 310 computers,
only 4 peripheral chip selects (PCS04-01) are used. PCSOO[O] is decoded but has
no connection.
PDSl-0(0) The Peripheral Data Strobe (PDS) signals are asserted by the bus master to select
which bytes of the 16-bit data bus are to be enabled. PDSO[l] enables byte O ( data
bits 15-08); PDSl[l] enables byte 1 (data bits 07-00).
PDTACK[O) The Peripheral Data Acknowledge (PDTACK) signal is asserted by the bus slave to
acknowledge the receipt of valid write data or to indicate the presence of valid read
data on the I/0 bus. A feature card that has requested a system board CPU
interrupt also asserts the PDTACK in response to the Peripheral Interrupt
Acknowledge (PIAK) asserted by the system board.
PP AS[O)
The Peripheral Physical Address Strobe (PP AS) is asserted by the bus master to
indicate the presence of a valid physical address on the I/0 bus.
PR[l JW[OJ The Peripheral Read/Write (PR[l ]W[O]) signal is asserted or negated by the bus
master to indicate the type of access (read or write). A logic 1 indicates a read
operation; a logic O indicates a write operation.
PS1ZE16[0)
The PSIZE16 signal specifies the width of the bus interface for the feature card as
either 16 bits (logic 0) or 8 bits wide (logic 1). For 8-bit peripherals, data will be
transferred on data bits 07-00.
RQRST[O) The Request System Reset (RQRST) signal is asserted by a feature card to request a
system reset.
SYSRST[O) The System Reset (SYSRST) signal is asserted in response to a manual reset, system
powerup sequence, a software request, or the RQRST[O] signal.
PBRQ[O)
The Peripheral Bus Request (PBRQ) is asserted by a feature card to gain access to
the I/0 bus. The bus arbitration circuits on the system board handle the bus
request.
PBACKI[OJ/PBACKO[O)
The system board asserts a Peripheral Bus Acknowledge Output (PBACKO) signal
to acknowledge a feature card bus request. This signal is daisy-chained to all
FUNCTIONAL DESCRIPTION 3-15