AT&T 3B2/300 Technical Reference Manual page 348

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TM
ET
Bit 02 is the Trace Mask (TM) bit. This read-only field masks the Trace Enable (TE)
bit for the duration of one instruction to avoid a trace trap. The TM bit is set [1] at
the start of every instruction. The TM bit is cleared [O] as part of every
microsequence that performs a context switch, a return from gate, or when any
fault/interrupt is processed.
Bits 01 and 00 are the Exception Type (ET) bits. The ET field is used with the
Internal State Code (ISC) field (PSW06-03) to distinguish between exceptions of
the same type. The code for bits 01 and 00 are as follows.
BIT 01 BIT 00 DESCRIPTION
0 0 ON RESET EXCEPTION
0 1 ON PROCESS EXCEPTION
1
0 ON STACK EXCEPTION
1 1 ON NORMAL EXCEPTION
FUNCTIONAL DESCRIPTION 3-95