AT&T 3B2/300 Technical Reference Manual page 446

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Application Control Register
The Application Control Register (ACR) bits are defined in the following table. All GPSC card
resets clear ALL bits in this register to logical "O."
NOTES:
BIT SIGNAL
FUNCTION
0 DIVAOO[l] Port A Clock Division
1 DIVAOl[l] (Note 1)
2 TCKOUTA[O] Tx Clock Out Enable Port A Write
"O" to enable output.
3 NEWSJGA[O] Port A New Signal
4 DIVBOO[l] Port B Clock Division
5
DIVB01[1] (Note 1)
6
TCKOUTB[O] Tx Clock Out Enable Port B Write
"O" to enable output.
7 NEWSIGB[O] Port B New Signal
8 EECS[l]
EEPROM Chip Select (Note 2)
9
EECLK[l] EEPROM Serial Clock
10 EEDIN[l] Serial Data Input To EEPROM
11 EEDOUT[l] Serial Data Output From EEPROM
12
TCLKINA[O]
Transmit Clock Input Enable (CH A)
Write "O" to enable clock input.
13 TCLKINB[O] Transmit Clock Input Enable (CH B)
Write "O" to enable clock input.
14
FAIL[l]
PFAIL-Activates PFAILO
15
-
Unassigned
1. Transmit clock division is required in some instances.
The transmit clock division is designated as follows:
D1Vx01 DIVxOO
0 0 No Division
0 1 Clock divided by 16 before output
0 Clock divided by 32 before output
Undefined
2. Timing of EEPROM accesses are controlled by software.
FUNCTIONAL DESCRIPTION 3-193