AT&T 3B2/300 Technical Reference Manual page 466

Table of Contents

Advertisement

- - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Peripheral Control and Status Register
The CTC card contains an 8-bit Peripheral Control and Status Register (PCSR) addressable on the
lower data byte of the 1/0 address (Ox 048F-Ox 0488). Each address corresponds to a single bit of the
PCSR. These bits are reset by an 80186 Microprocessor read or write access except for PCSR6 that is
controlled by the Bus Abort Feature (BAF).
CTC PERIPHERAL CONTROL AND ST A TUS REGISTER
BIT
DESCRIPTION
7
REQUEST SYSTEM BOARD CPU INTERRUPT: PCSR7[0] maps to the
1/0
bus signal
PINTO[O] and is asserted by the PORTS firmware. When negated [l] by hardware, the
interrupt has been acknowledged by the system board CPU. When asserted [OJ, the interrupt
request is pending. A system reset negates the bit to a logic 1 (interrupt acknowledged).
Addressing PCSR7[1] (Ox 048F) clears (negates) the bit.
6
1/0 BUS LOCKED: This bit is used for the BAF. Bit 6 is set by hardware when the 80186
Microprocessor is delayed in accessing main memory and must be cleared by firmware.
During normal operation, PCSR6 is cleared by the 80186 Microprocessor addressing PCSR6
unless a "dummy" read is pending. Addressing PCSR6 (Ox 048E) clears (negates) the bit.
5
Used to control Asynchronous Data Ready (ARDY[l]).
4
Not used by CTC.
3
Not used by CTC.
2
Not used by CTC.
1
CLEAR INTI: This 80186 Microprocessor interrupt is set by a system board CPU access of the
CTC PCSR (attention interrupt). PCSRl is cleared during the interrupt service routine by an
access of the 80186 Microprocessor address Ox 0489. Following a system reset the state of
PCSRl is undefined and is cleared by the CTC firmware.
0
CLEAR INTO: This 80186 Microprocessor interrupt is set by an access of the CTC ID /Vector
Register (except on an interrupt acknowledge cycle). This interrupt is the SYSGEN and Express
Queue interrupt. Bit O is cleared during the interrupt service routine by an access of the 80186
Microprocessor address Ox 0488. Bit O is undefined on powerup and is cleared by the
firmware.
FUNCTIONAL DESCRIPTION
3-213

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents