AT&T 3B2/300 Technical Reference Manual page 374

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Control, Status, and Error Register
The Control, Status, and Error Register (CSER) is a 32-bit register. It provides low-level access to
the system board logic circuits. The CSER controls and monitors various system functions. All bits are
clearable or setable under software control. All CSER bits are writable by software using a full word
write to the address of that bit, half-word write to the given address plus 2, or a byte write to the
address plus 3.
The CSER bit assignments and access information are shown in Figure 3-34. The 32 bits are
divided into four groups of 8 bits. A read operation at the address of any bit in a group places the
whole group on data bits 07-00 so that it remains constant throughout the read cycle. The CSER is
NOT cleared by a hardware reset. The state of the CSER after a write operation is dependent only on
the address; the data written is a "don't care" bit. The contents of the CSER are part of the error report
output by the /etc/errdump command. The CSER is identified as "cser" in the error report.
FUNCTIONAL DESCRIPTION 3-121