AT&T 3B2/300 Technical Reference Manual page 373

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
Read Only Memory
The Erasable Programmable Read Only Memory (EPROM) is configured to yield 128K bytes of
ROM. For the CM518A/B System Boards, the ROM is formed using four 32K by 8 EPROM integrated
circuits (27256's). For the CM518C System Board, the ROM is formed using two 64K by 8 EPROM
integrated circuits (27512's). The starting address of ROM is Ox 00000000.
Timers
The timers include the following:
• Time of day (MM58274)
• Interval (INTEL 82C54)
• Sanity (INTEL 82C54)
• Bus (INTEL 82C54).
The interval, sanity, and bus timers are implemented in an INTEL 82C54 timer chip.
Clock/Calendar Timer. The Clock/Calendar Timer (MM58374) calculates current date to tenths of
a second. The timer is controlled by a 32.768-kHz oscillator. The timer features automatic leap year
calculation, protection for read access when changing data, and low standby current (2.2 volt,
10 microamperes). The accuracy is determined by the 32.768-kHz crystal with a 0.003 percent
tolerance (
±
1.3 minutes per month).
Periodic Timer.
The Interval Timer (Timer 1) has a 100 kHz (CLKTA[l]). The Inhibit UNIX
Interval Timer (INHUIT) CSER bit (bit 7) inhibits operation of this timer. When the timer expires, the
UNIX Interval Timer Time-out (UITT) bit (bit 0) of the CSER is set and a level 15 interrupt is sent to the
Interrupt Decoder.
Sanity Timer.
The Sanity Timer (Timer 0) is a count down timer that is normally reset by software
before it reaches zero. The time base is 10 kHz (CLKTB[l ]). The Inhibit System Sanity Timer
(INHSST) CSER bit (bit 8) inhibits operation of this timer. When the Sanity Timer reaches zero, an
error signal turns on the Diagnostic indicator, a level 15 interrupt is sent to the Interrupt Decoder, and
the Sanity Timer Time-out (SANTO) bit (bit 29) is set in the CESR. The CSER bit 29 is cleared by
writing to address Ox 00044000. This count down timer is started when the power switch is pressed to
OFF. System software must read the 82C54 package to determine whether Sanity Timer (Timer 0) or
the Bus Timer (Timer 2) timed out.
Bus Timer.
The Bus Timer (Timer 2) is as the Unbuffered Bus (UBus) access timer. The time base
is 500 kHz (CLK02[1 ]). The Inhibit UBus Timer (INHUBT) CSER bit (bit 10) inhibits operation of this
timer. The UBus timer starts counting when the virtual address strobe is asserted. The UBus timer is
reset when the virtual address strobe is negated. If the timer is not reset within the programmed period
(1 millisecond), an error signal turns on the Diagnostic indicator, a level 15 interrupt is sent to the
Interrupt Decoder, and the UBus Timer Time-out bit (bit 26) is set in the CSER. The CSER bit 26 is
cleared by writing to address Ox 00044000. System software must read the 82C54 package to determine
whether Sanity Timer (Timer 0) or the Bus Timer (Timer 2) timed out.
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