AT&T 3B2/300 Technical Reference Manual page 473

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
Peripheral Control and Status Register
The XDC card contains an 8-bit Peripheral Control and Status Register (PCSR) which is addressable
on the lower data byte of the
1/0
address (Ox 048F-Ox 0488). Each address corresponds to a single bit
of the PCSR. These bits are reset by an 80186 Microprocessor read or write access.
XDC PERIPHERAL CONTROL AND ST A TUS REGISTER
BIT DESCRIPTION
7
REQUEST SYSTEM BOARD CPU INTERRUPT: PCSR7[0] maps to the 1/0 bus signal
PINTl[O] and is asserted by the XDC firmware. When negated [1] by hardware, the interrupt
has been acknowledged by the system board CPU. When asserted [OJ, the interrupt request is
pending. A system reset negates the bit to a logic 1 (interrupt acknowledged). Addressing
PCSR7[1] (Ox 048F) clears (negates) the bit.
6
PCSR6 is not registered; however, the PCSR6 address (Ox 048E) is used to set PCSR4.
Addressing PCSR6 asserts PCSR4. This provides the XDC the ability to reset the hard disk
controller under XDC firmware control.
5 Used to control Asynchronous Data Ready (ARDY[l ]).
4 HARD DISK CONTROLLER RESET: This bit resets the hard disk controller when asserted
[1]. Addressing PCSR4 (Ox 048C) clears the bit and negates the reset. The hard disk controller
is reset by either a system reset or by the 80186 Microprocessor addressing PCSR6 (Ox 048E)
which asserts PCSR4.
3
Not used by the XDC card. Addressing PCSR3 (Ox 048B) clears (resets) the bit.
2 CLEAR INT2: This 80186 Microprocessor interrupt is set by the hard disk controller on seek
end, disk ready change, seek error, or equipment check conditions. PCSR2 is cleared during
the interrupt service routine by an access of the 80186 Microprocessor address Ox 048A.
1
CLEAR INTl: This 80186 Microprocessor interrupt is set by a system board CPU access of the
XDC PCSR (attention interrupt). PCSRl is cleared during the interrupt service routine by an
access of the 80186 Microprocessor address Ox 0489. Following a system reset the state of
PCSRl is undefined and is cleared by the XDC firmware.
0
CLEAR INTO: This 80186 Microprocessor interrupt is set by a system board CPU access of the
XDC ID/Vector Register (except on an interrupt acknowledge cycle). This interrupt is the
SYSGEN and Express Queue interrupt. Bit O is cleared during the interrupt service routine by
an access of the 80186 Microprocessor address Ox 0488. Bit O is undefined on powerup and is
cleared by the XDC firmware.
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