AT&T 3B2/300 Technical Reference Manual page 272

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System Board Peripheral Controller Write Operation.
Figure 3-7 shows the system board
peripheral controller write operation. A system board CPU write operation of a peripheral controller
(feature card) starts with the Peripheral Read/Write signal (PRl WO) (Write=O), Peripheral Physical
Address signals (PPA23-00[1 ]), and the Peripheral Card (Chip) Select signal (PCS[O]) occurring
simultaneously. The selected feature card sends the PSIZEI6[0] signal to define its data width (8
bits=l, 16 bits=O) in response to the PCS[O] signal. The system board CPU sends the Physical Address
Strobe (PP AS[O]) to the feature card when the address lines (PP A23-00[l]) are stable. The system board
CPU puts the data to be written to the feature card on the Peripheral Data bus (PDIS-00[1 ]). The
Peripheral Data Strobes (PDSOl-00[0]) are sent to the feature card to indicate which data byte(s) were
placed on the 16-bit data bus. The feature card sends the Peripheral Data Transfer Acknowledge
(PDTACK[O]) signal after getting the write data from the data bus. As with a read operation, the system
board releases the bus after receiving the PDTACK[O] signal by driving the strobes inactive and
tri-stating the bus. The feature card relinquishes the bus when it sees the inactive (high=l) strobes.
FUNCTIONAL DESCRIPTION 3-19