AT&T 3B2/300 Technical Reference Manual page 297

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
WE 32100
MICROPROCESSOR
WAIT STATE
AND STROBE
GENERATION
CIRCUITS
DRAM
CONTROLLER
AND ARBITER
CIRCUITS
TOD CLOCK
ADDRESS
DECODER
VCC (+SV)
GROUND
[
(
(
NO CONNECTION (NC)
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-
-
-
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ADDRESS BITS 31-00[1]
DATA BITS 31-00[1]
FAULT (FLT[O])
READ/WRITE (R[ll/W[O])
DATA READY (DRDY[O])
DATA SHADOW (DSHAD[O])
DAT A SIZEO (DSIZEO[l])
DATA SIZE! (DSIZEl[l])
ABORT[O]
ACCESS STATUS3-0 (SAS3-0[!]
ADDRESS STROBE (AS[O])
CLK23[! ]. CLK34[1]
DAT A STROBE (DS[O])
EXECUTION LEVELl-0 (XMDl-0[1])
RESET[O]
VIRTUAL ADDRESS (VAD[O])
SYNCHRONOUS READY (SRDY[O])
SYNCHRONOUS READY (SRDY[O])
EARLY ADDRESS STROBE (EPAS[O])
R AND M BITS WRITE (RMW[O])
MMU CYCLE INITIATE (MCYCLEI[O])
PHYSICAL ADDRESS STROBE (PAS[O])
DATA TRANSFER ACKNOWLEDGE (DTACK[O])
CHIP SELECT (MSC[O])
DATA STROBE (DS[O])
HIGHZ[O]
TRANSLATION CHIP SELECT A (TCSA[O])
TRANSLATION CHIP SELECT B (TCSB[O])
CACHEABLE (CABLE[O])
CONTIGUOUS SEGMENT (CONTIG[O])
Figure 3-15: WE 32101 MMU Interconnection Diagram
3-44 TECHNICAL REFERENCE MANUAL
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WE 32101
MEMORY
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MANAGEMENT
UNIT
r
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.