AT&T 3B2/300 Technical Reference Manual page 326

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Dual Port Dynamic Random Access Memory Controller
General.
The system main memory is a Dual Port Dynamic Random Access Memory (DPDRAM).
The system board CPU uses one port and the other memory port is shared by the feature cards and
integral Direct Memory Access Controller (DMAC). The DPDRAM Controller provides the system
board CPU direct access to the I/0 bus without passing through the RAM. The Dynamic Random
Access Memory (DRAM) Controller handles the exchange of data and address information between the
I/0 bus and the system board CPU when operating in the "bypass mode."
Figure 3-24 is a functional block diagram of the DPDRAM Controller. The DRAM Controller for
the DPDRAM is divided into the following functional areas:
• Address Generation Logic (address multiplexer)
• Request Generator
• Arbitration Logic
• Memory Refresh Logic
• Sequencer
• Bypass Logic
• Data Byte Rotate Unit Logic
• Parity Generation and Checking Logic.
Each of these functional areas is briefly described in the following paragraphs.
FUNCTIONAL DESCRIPTION 3-73