AT&T 3B2/300 Technical Reference Manual page 504

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Peripheral Control and Status Register
The EPORTS card contains an 8-bit Peripheral Control and Status Register (PCSR) addressable on
the lower data byte of the 1/0 address (Ox 048F-Ox 0488). Each address corresponds to a single bit of
the PCSR. These bits are reset by an 80186 Microprocessor read or write access except for PCSR6 that
is controlled by the Bus Abort Feature (BAF).
EPORTS PERIPHERAL CONTROL AND STATUS REGISTER
BIT DESCRIPTION
7
REQUEST SYSTEM BOARD CPU INTERRUPT: PCSR7[0] maps to the 1/0 bus signal
PINTO[O] and is asserted by the EPORTS firmware. When negated [1] by hardware, the
interrupt has been acknowledged by the system board CPU. When asserted [OJ, the interrupt
request is pending. A system reset negates the bit to a logic 1 (interrupt acknowledged).
Addressing PCSR7[1] (Ox 048F) clears (negates) the bit.
6
1/0 BUS LOCKED: This bit is normally used for the BAF. EPORTS does not use PCSR6.
5 Used to control the End-of-Page 3 (EOP3) interrupt. Addressing PCSR6 (Ox 048D) clears
(negates) the bit.
4 Used to control End-of-Page 2 (EOP2) interrupt. Addressing PCSR6 (Ox 048C) clears (negates)
the bit.
3 Used to control End-of-Page 1 (EOPl) interrupt. Addressing PCSR6 (Ox 048B) clears (negates)
the bit.
2 Used to control End-of-Page O (EOPO) interrupt. Addressing PCSR6 (Ox 048A) clears (negates)
the bit.
1
CLEAR INTl: This 80186 Microprocessor interrupt is set by a system board CPU access of the
EPORTS PCSR (attention interrupt). PCSRl is cleared during the interrupt service routine by
an access of the 80186 Microprocessor address Ox 0489. Following a system reset the state of
PCSRl is undefined and is cleared by the EPORTS firmware.
0 CLEAR INTO: This 80186 Microprocessor interrupt is set by an access of the EPORTS
ID/Vector Register (except on an interrupt acknowledge cycle). This interrupt is the SYSGEN
and Express Queue interrupt. Bit O is cleared during the interrupt service routine by an access
of the 80186 Microprocessor address Ox 0488. Bit O is undefined on powerup and is cleared by
the firmware.
FUNCTIONAL DESCRIPTION 3-251