AT&T 3B2/300 Technical Reference Manual page 345

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
General Purpose Registers (r23-r16, r8-r0)
Seventeen general-purpose registers are used for accumulation, addressing, and for temporary data
storage. They can be used in any addressing mode by any program (privileged or nonprivileged).
Registers r2, rl, and rO are also implicitly used by certain other data transfer instructions and by certain
operating system instructions. Registers r2, rl, and rO are also used by the CPU as a scratch pad. The
contents of registers r8-r3 are part of the error report output by the /etc/errdump command.
Frame Pointer Register (r9)
The Frame Pointer (FP) register (r9) contents point to the beginning address (location) in the stack
of a function's local variables. The contents of register r9 are part of the error report output by the
/etc/errdump command.
Argument Pointer Register (r10)
The Argument Pointer (AP) register (rlO) contents point to the starting address (location) in the
stack where a set of arguments for a function have been pushed. The contents of register rlO are part
of the error report output by the
/etc/errdump command. This register is identified as "oap" in the
error report.
Processor Status Word Register (r11)
The Processor Status Word (PSW) register (rll) contains information that determines the current
execution state of the CPU. The PSW register is kernel level privileged. The contents of PSW register
(rl l) are part of the error report output by the
/etc/errdump command. This register is identified as
"psw" in the error report. The format of the PSW register is as follows.
PROCESSOR ST A TUS WORD REGISTER
BITS 31-30 29 28 27 26 25 24 23 22 21-18 17 16-13 12-11 10-09 08 07 06-03
02 01-00
FIELD UNUSED EA EX/UC
AR
X CFD QIE CD OE NZVC TE IPL CM PM R I !SC TM ET
The PSW register fields are defined in the following paragraphs.
UNUSED
EA
EX/UC
AR
X
CFD
QIE
Bits 31-30 are not used and are always cleared [OJ.
Bit 29 is the Arbitrary Byte Alignment Enable (EA) bit. When set [1 J, the arbitrary
byte alignment is enabled allowing the CPU to read or write word and half-word
data from any byte boundary. When clear [OJ, arbitrary byte alignment is disabled
and the alignment fault detection is enabled. The bit is cleared on external reset.
Bit 28 is the Normal Exception and User Call (EX/UC) option bit. When set [l J,
normal exception procedures are identical to process switches and user-initiated
process switches are enabled. The bit is cleared on external reset.
Bit 2 7 is the Additional Register Save (AR) bit. When set [1 J, this bit enables the
additional 8 registers (r23-r16) to be saved during a process switch if no block
moves are being executed. The bit is cleared on external reset.
Bit 26 is the Extend Carry /Borrow (X) bit. This bit represents the condition code for
the binary coded decimal operations. The bitcan only be set if there is a carry or
borrow from a binary coded decimal arithmetic operation. The bit is reset if there is
no carry or borrow.
Bit 25 is the Cache Flush Disable (CFO) bit. When set [1 J, instruction cache
flushing is disabled when a new process is loaded. When clear [OJ, the contents of
the cache are flushed when a new process is loaded.
Bit 24 is the Quick Interrupt Enable (QIE) bit. When set [1 J, the quick interrupt
handling facility is enabled. When clear [OJ, an interrupt causes a process switch to
a full interrupt processing sequence.
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