AT&T 3B2/300 Technical Reference Manual page 362

- - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Auxiliary Status Register
The Auxiliary Status Register (ASR) is used to do the following:
• Control the remainder operation (partial remainder bit)
• Signal the state of an operation (result available bit)
• Disable and record exceptions (mask and sticky bits)
• Control rounding of results (round control bits)
• Record condition codes (negative and zero bits).
The negative, zero, inexact, and integer overflow bits in the ASR match the condition codes in the
PSW register of the CPU. This allows the bits to be copied into the PSW as part of the coprocessor
status access and to be easily tested by the CPU. The format of the ASR is as follows.
AUXILIARY
STATUS REGISTER (31-16)
BITS
31 30 - 26
25 24 23 - 22 21 20 19 18 17 16
FIELD
RA UNUSED ECP NTNC RC N
z
JO PS
csc
uo
AUXILIARY STATUS REGISTER
(15-00)
BITS
15 14 13 12
11 10
09 08 07 06 05 04 03-01 00
FIELD
WF IM OM UM
QM
PM JS OS
us
QS
PR
uw
VER FE
The ASR fields are defined in the following paragraphs.
UNUSED
RA
ECP
NTNC
Bits 30-26 are not used. These bits are returned as zeros when read.
Bit 31 is the Result Available (RA) bit. It is cleared at the beginning of an operation
and set
[1]
when the operation result is available. During the quiescent state, the
RA bit is set.
Bit 25 is the Exception Condition Present (ECP) bit.
It
is set [1) if any one of the
floating point exception conditions except "inexact" is present. The ECP bit is
cleared [O].
Bit 24 is the Nontrapping Not a Number (NAN) Control (NTNC) bit. Bit 24 is
tested when an invalid operation exception occurs and bit 14 (IM) is cleared. If
bit 24 is set, an exception occurs and bit 09 (IS) is set.
FUNCTIONAL DESCRIPTION 3-109