AT&T 3B2/300 Technical Reference Manual page 439

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
Input/Output Bus Interface
The bus interface provides the following functions:
• I/0 Control-Provides the functionality of recognizing, controlling, and responding to the I/0
bus states. The actions are initiated by the 3B2 CPU or the 80186 Microprocessor.
• Address Drivers-Provides 24 bits of address information over the I/0 bus.
o 17 bits of bus address directly from the 80186 Microprocessor
o 7 bits as Page Register.
• Data Transceivers-Holds ID information and Interrupt vectors as well as buffering bidirectional
data to and from the I/0 bus. There is a byte swap performed with processing unit data bits 0
through 7 being mapped to I/0 data bits 8 through 15 and data bits 8 through 15 being mapped
to I/0 data bits O through 7.
• 3B2 Computer Invoked Interrupts-The 3B2 computer may cause interrupts on the processing
unit by accessing particular locations (location 1) in the processing unit I/0 space.
Nonvolatile Memory
The processing unit supports up to 32K bytes of Erasable Programmable Read Only Memory
(EPROM) in the form of two INTEL 27128 PROMs.
Volatile Memory
The processing unit is equipped with 256K bytes of Static Random Access Memory (SRAM). This
memory is in the form of two 128K by 16-bit SRAM modules.
External Interface
The external interface is handled through the FIB. The signals for the FIB are passed through the
two 40-conductor ribbon cables. These signals are grouped as follows:
• Address lines
• Data lines
• Control lines
• Timer Input/Output.
Address Signals
The processing unit provides all 20 address lines to the FIB. These lines are buffered to allow
driving from an external interface. The control of the lines is determined by the HOLDAl signal. A
low (0) indicates that the processing unit is driving the address bus and a high (1) indicates that the
external board is generating the address information.
Data Lines
The processing unit provides all 16 data bits. The direction control of these signals is driven by the
IDTlRO signal, which is driven by the processing unit or the external board.
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