AT&T 3B2/300 Technical Reference Manual page 444

- - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
INTEL 80186 Microprocessor
The intelligence of the GPSC card is provided by an INTEL 80C186, 16-bit microprocessor
operating at 16 MHz. Some of the microprocessor features used for the GPSC card are described in the
following paragraphs. Figure 3-60 shows the GPSC card address map.
DMA Channels
Four independent 4-bit Page Registers, one for each channel, are provided to allow access to the
entire DRAM address range. All four are used by supporting both transmit and receive on each port.
Note that for Direct Memory Access (OMA), DRAM is partitioned into 64-kilobyte segments and that a
single OMA job cannot cross the segment boundaries.
Channel O and 1 are Receive Channel A and Transmit Channel A, respectively. Channel 2 and 3
are Receive Channel Band Transmit Channel B, respectively.
Interrupt Controller
The internal Interrupt Controller of the 80C186 Microprocessor is programmed to accept five
separate interrupts: INT3 through INTO, and NMI. Interrupts INTO and INTI are reserved for common
1/0 firmware use. INT2 is dedicated to the 82C37 A OMA Controller. INT3 is a combined
85C30/8536 interrupt. Nonmaskable Interrupt (NMI) is used by the common 1/0 firmware to control
the Bus Abort Feature (BAF).
Internal Timers
Timer O is a DRAM refresh timer. Timer 1 controls the BAF. Timer 2 is used as a general purpose
timer.
The 8536 Counter/Timer Parallel 1/0 (CT/PIO) device contains three independent 16-bit
counter/timers. Timers 1 and 2 are the clock tick counters for Channel B transmit clock and Channel A
transmit clock, respectively. Timer 3 is the zero counter for Channel A.
FUNCTIONAL DESCRIPTION 3-191