AT&T 3B2/300 Technical Reference Manual page 10

List of Figures
Figure 2-46: CM195AC/CM195AD Datakit VCS Interface Card Layout
2-146
Figure 2-47:
CMl 95AE GPSC Card Layout 2-148
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Figure 2-48: CMl 95A Y EPORTS Card Layout .
2-150
Figure 2-49: CMl 95B PORTS Card Layout (Early Production) 2-152
Figure 2-50:
CM195B-7 PORTS Card Layout 2-153
Figure 2-51: CMl 95BA PORTS Card Layout
2-156
Figure 2-52:
CM195H CTC Card Layout 2-158
Figure 2-53: CMl 95K XDC Card Layout 2-160
Figure 2-54:
CMl 95T ISC Card Layout 2-162
Figure 2-55: CMl 95U ST ARLAN Interface Card Layout
2-164
Figure 2-56: CM195W SCSI Host Adapter Card Layout 2-166
Figure 2-57: CMl 95Y EPORTS Card Layout
2-168
Figure 2-58: CM521A Differential SCSI Host Adapter Card Layout 2-170
Figure 2-59: CM522A VCACHE Card Layout
2-172
Figure 2-60: CM524A PE Card Layout 2-174
Figure 2-61: CM525B VMEbus Card Layout
2-176
Figure 2-62: CM527A MPE Card Layout 2-178
Figure 2-63: Version 2 Computer Backup Battery Supply Layout
2-218
Figure 2-64: 3B2/500 Computer Backup Battery Supply Position 2-219
Figure 2-65: 3B2/600, 700, and 1000 Computer Backup Battery Supply Position 2-220
Figure 3-1: Version 2 Computer-High-Level Functional Block Diagram
3-3
Figure 3-2: Version 3 Computer-High-Level Functional Block Diagram 3-7
Figure
3-3: Version 2 Computer Address Spectrum
3-10
Figure 3-4: Version 3 Computer Address Spectrum
3-11
Figure
3-5:
Input/Output Bus Signals 3-14
Figure 3-6: System Board Peripheral Controller Read Operation 3-18
Figure 3-7: System Board Peripheral Controller Write Operation
3-20
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Figure 3-8: Peripheral Controller Main Memory Read Operation 3-22
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Figure 3-9: Peripheral Controller Main Memory Write Operation 3-24
Figure 3-10: Self-Configuration - Powerup Sequence 3-27
Figure 3-11: Self-Configuration - Manual Boot Sequence 3-28
Figure 3-12: Self-Configuration Process 3-30
Figure 3-13:
Version 2 3B2 Computer System Board-Functional Block Diagram
3-33
Figure 3-14: System Board CPU-Functional Block Diagram 3-36
Figure 3-15:
WE 32101 MMU Interconnection Diagram
3-44
Figure 3-16: WE 32101 MMU Block Diagram 3-45
Figure 3-17: MMU Internal Address Spectrum 3-51
Figure 3-18: Virtual Address to Physical Address Translation for Contiguous Segments 3-53
Figure 3-19:
Virtual Address to Physical Address Translation for Paged Segments
3-54
Figure 3-20: WE 32106 Math Acceleration Unit-Functional Block Diagram 3-56
Figure 3-21: Chip Select and Control Signals Address Decode 3-64
Figure 3-22: Version 2 System Board CSR Bit Assignments 3-68
Figure 3-23: System Board Interrupt Assignments 3-70
Figure 3-24: Dual Port Dynamic Random Access Memory Controller-Functional Block
Diagram 3-74
Figure 3-25: Data Byte Selection Summary . 3-77
Figure 3-26: Direct Memory Access Subsystem-Functional Block Diagram 3-79
Figure 3-27: Version 3 3B2 Computer System Board-Functional Block Diagram 3-87
Figure 3-28:
CM518B/C System Board CPU-Functional Block Diagram 3-90
Figure 3-29: WE 32201 MMU Interconnection Diagram 3-98
Figure 3-30: MMU Internal Address Spectrum 3-104
Figure 3-31: Virtual Address to Physical Address Translation for Paged Segments 3-106
Figure 3-32: WE 32206 Math Acceleration Unit-Functional Block Diagram . 3-108
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vi TECHNICAL REFERENCE MANUAL