AT&T 3B2/300 Technical Reference Manual page 292

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NZVC
TE
IPL
CM
PM
R-1
Bits 21-18 are used to represent four condition codes that reflect the status of the
most recent instruction execution. The codes are tested using conditional branching
instructions and indicate the following when set.
Bit 21(1] - Negative (N)
Bit 20[1] - Zero (Z)
Bit 19[1] - Overflow (V)
Bit 18[1] - Carry (C)
Bit 17 is the Trace Enable (TE) bit. When set [1 ], the trace function is enabled,
causing a trace trap to occur after execution of the next instruction. Debugging and
analysis software use the trace facility for single-stepping a program.
Bits 16-13 are the Interrupt Priority Level (IPL) bits. Bit 13 is the least significant
bit. Fifteen interrupt levels are available. An interrupt, unless it is a nonmaskable
interrupt, must have a higher priority than the current registered IPL bits in order
for the interrupt to be acknowledged. Level 0000 indicated that any of the fifteen
interrupt priority levels (0001 through 1111) can interrupt the CPU. A registered
IPL of 1111 indicates that no interrupts (except a nonmaskable interrupt) can
interrupt the CPU.
Bits 12 and 11 are the Current Execution Mode (CM) bits. The code for bits 12 and
11 are as follows.
BIT 12 BIT 11 DESCRIPTION
0 0 KERNEL LEVEL
0 1 EXECUTIVE LEVEL
1 0
SUPERVISOR LEVEL
1 1 USER LEVEL
Bits 10 and 09 are the Previous Execution Mode (PM) bits. The code for bits 10 and
09 are as follows.
BIT 10 BIT 09 DESCRIPTION
0 0
KERNEL LEVEL
0 1 EXECUTIVE LEVEL
1
0 SUPERVISOR LEVEL
1 1
USER LEVEL
Bits 08 and 07 are the Register-Initial Context (R-I) bits. These bits control the CPU
context switching strategy. The I bit (bit 07) determines if a process executes from
initial (I=l) or intermediate saved context (I=O). The R bit (bit 08, read only)
determines if the registers of a process should be saved during a process switch
(R=l).
FUNCTIONAL DESCRIPTION 3.39