AT&T 3B2/300 Technical Reference Manual page 342

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Central Processing Unit
The Central Processing Unit (CPU) on a CM518A System Board is a WE 32100 Microprocessor.
The CPU on a CM518B/C System Board is WE 32200 Microprocessor. The WE 32100 chipset is
covered in the "CM190A/ED-4C637-30 System Board" section of this chapter for Version 2 system
boards. Refer to that section for detailed information on the CPU /MMU /MAU chips of the CM518A
System Board. The remainder of this section will pertain to the WE 32200 chipset used on the
CM518B/C System Boards.
The CPU provides separate 32-bit address and data busses. The 32-bit address bus is used to
address memory or peripherals mapped into the system memory space using physical or virtual
addresses. Data is read to or written from the CPU over the 32-bit, bidirectional, data bus in either
word (32-bit), half-word (16-bit) or byte (8-bit) widths. The CPU automatically expands bytes and
half-words to words (32 bits) for processing. Zeros fill the high-order bits for unsigned operations. For
signed operations, the sign bit (bit 7 for bytes, bit 15 for half-words) fills the high-order bits.
Instruction execution speed is enhanced by an internal instruction queue and an internal instruction
cache. The instruction queue is an 8-byte, First-In-First-Out (FIFO) queue that stores prefetched
instructions. The instruction cache is a 64-word cache used to increase the CPU performance by
reducing the external memory reads for instruction fetches. When an instruction fetch from memory
occurs, the instruction data is placed in both the instruction queue and the instruction cache. If the
instruction data is needed again, it is read from the cache rather than from external memory.
Functionally, the system board CPU consists of bus interface control, main controller, fetch unit,
and the execute unit circuits. Figure 3-28 shows a functional block diagram of the CM518B/C System
Board CPU.
FUNCTIONAL DESCRIPTION 3-89