AT&T 3B2/300 Technical Reference Manual page 328

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Address Generation Logic.
The Address Generation Logic latches the stable virtual address during
virtual to physical address translation. Since the 11 least significant bits of a virtual address and a
physical address are identical, CPU-memory read accesses are started when the CPU presents a stable
virtual address. The early start using the 11 least significant address bits enhances system performance.
Request Generator. The Request Generator synchronizes the bus requests with the system clock
and passes the synchronized data requests to the Arbitration Logic. The Request Generator passes four
types of requests to the Arbitration Logic. These requests are listed below:
Memory Refresh (REFREQ[l ])
The memory refresh request is automatically generated every 16 microseconds.
Input/Output-DRAM (LPBRQ[l ])
The input/output-memory request can originate from a feature card (PBRQ[O]) or
from the Direct Memory Access Controller (XPBRQ[O]). The request is passed to the
Arbitration Logic as LPBRQ[l].
CPU-DRAM (CPUMEMRQ[l])
The CPU-memory read or write operation requests are sent to the Arbitration
Logic as CPUMEMRQ[l].
CPU-Input/Output (CPUIORQ[l ])
The CPU-input/output exchange request is asserted by the Address Decoder
(CREQ[O]) and is sent to the Arbitration Logic as CPUIORQ(l ].
Arbitration Logic.
The Arbitration Logic determines which requests for memory access are to be
acknowledged. These access requests from highest to lowest priority follow:
• Memory Refresh (highest priority)
• Input/Output-DRAM
• CPU-DRAM
• CPU-Input/Output (lowest priority).
Memory Refresh Logic.
The refresh of the DRAM is done one row at a time every
16 microseconds. The Request Generator is a counter and request flip-flop. Refresh requests are
derived from the 1-MHz clock and occur every 16 microseconds. The refresh request increments the
refresh address counter.
A memory refresh operation can occur between input/output to DRAM block transfers or between
the read and write halves of a CPU /MMU interlocked operation. Refresh operations continue during
reset sequences to retain any data which existed before the reset.
Sequencer.
The Sequencer generates the control signals (strobes) for the access operations enabled by
the Arbitration logic. The Sequencer is a Field Programmable Logic Array (FPLA) and flip-flop network
that combine to generate a variety of memory control signals.
FUNCTIONAL DESCRIPTION 3-75