AT&T 3B2/300 Technical Reference Manual page 333

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
Direct Memory Access Controller.
The integral Direct Memory Access Controller (DMAC) serves
the Dual Universal Asynchronous Receiver/Transmitter (DUART), integral Hard Disk Controller, and
the integral Floppy Disk Controller. The DMAC has four independent OMA channels. Each channel
has separate registers for mode control, current address, base address, current word count, and base
word count.
The DMAC generates a 16-bit address. An additional 8-bit Page Register is used for each of the
four OMA channels to provide OMA accessibility to the 22-bit DPDRAM. The most significant bit of
each Page Register is the read/write bit.
Dual Universal Asynchronous Receiver/Transmitter. The CONSOLE (UART 0) and CONTTY
(UART 1) are driven by a Signetics 2681-40 DUART. Each channel (0 and 1) provides the following
signals:
• Transmit data (TXD)
• Receive data (RXD)
• Data Carrier Detect (DCD)
• Data Terminal Ready (DTR).
Electrically, the DUART is on the peripheral bus with five other devices in the OMA Subsystem.
The UART has three output ports that are used for non-UART functions. These functions are listed
below:
• Control of off-board AC power relay via output port 2 (OP2) (PWRON[O]). The signal is high
during normal operations.
• Control of the Power indicator under certain operational conditions via output port 3 (OP3)
(GLEDON[l ]).
• Output port 4 (OP4) (UFEJCT[O]) is buffered and is sent to the floppy disk interface connector for
feature application.
• Output port 5 (OPS) (UFDSEL[O]) is buffered and sent to JlO as the Floppy Drive Select
(FDSEL[O]).
Integral Hard Disk Controller.
The integral Hard Disk Controller provides data and access control
for two Winchester disks. The interface is a ST-506 or "floppy disk type" interface at a data rate of
5 MHz. Data transfers are OMA controlled. All data lines are differential RS-422. The receiving end
of all data pairs is terminated by 100-ohm resistors. All control lines are open-collector. The receiving
end of all control lines are terminated by a resistor network of 220 ohms to VCC and 330 ohms to
ground.
The controller connects to data bus bits 07-00[1 ]. The chip enable is DSKCS[O]. The controller is
an NEC 7261 providing the following:
• Programmable track format
• Control two disk drives
• Parallel seek capability
• Multitrack and multisector capability
• Error checking and handling.
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TECHNICAL REFERENCE MANUAL