AT&T 3B2/300 Technical Reference Manual page 448

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Peripheral Control and Status Register
The GPSC card contains an 8-bit Peripheral Control and Status Register (PCSR) addressable on the
lower data byte of the 1/0 address (Ox 048F-Ox 0488). Each address corresponds to a single bit of the
PCSR. These bits are reset by an 80C186 Microprocessor read or write access except for PCSR6 that is
controlled by the Bus Abort Feature (BAF).
GPSC PERIPHERAL CONTROL AND ST A TUS REGISTER
BIT DESCRIPTION
7
REQUEST SYSTEM BOARD CPU INTERRUPT: PCSR7[0] maps to the l/0 bus signal
PINTO(O] and is asserted by the GPSC firmware. When negated (l] by hardware, the interrupt
has been acknowledged by the system board CPU. When asserted [OJ, the interrupt request is
pending. A system reset negates the bit to a logic 1 (interrupt acknowledged). Addressing
PCSR7(1] (Ox 048F) clears (negates) the bit.
6
1/0 BUS LOCKED: This bit is used for the BAF. Bit 6 is set by hardware when the 80C186
Microprocessor is delayed in accessing main memory and must be cleared by firmware.
During normal operation, PCSR6 is cleared by the 80C186 Microprocessor addressing PCSR6
unless a "dummy" read is pending. Addressing PCSR6 (Ox 048E) clears (negates) the bit.
5
RESERVED: A "1" indicates BAF occurred during OMA; a "O" indicates BAF occurred during
PIO.
4 BAF OCCURRED AND OMA BLOCKED: A BAF has occurred and the DMA has been
blocked from further use.
3 NONMASKABLE INTERRUPT: This bit indicates that the GPSC received a peripheral fault
during a OMA transfer or a fault from the debugger. Bit 3 is cleared during the interrupt
service routine by an access of the 80186 Microprocessor address Ox 0488.
2 CLEAR INT2-EOP: This 80C186 Microprocessor interrupt is set by the 8274 Dual Channel
Communications Chip. Bit 2 is cleared during the interrupt service routine by an access of the
BOC 186 Microprocessor address Ox 048A.
1 CLEAR INTI: This 80Cl 86 Microprocessor interrupt is set by a system board CPU access of
the GPSC PCSR (attention interrupt). PCSRl is cleared during the interrupt service routine by
an access of the SOC 186 Microprocessor address Ox 0489. Following a system reset the state of
PCSRl is undefined and is cleared by the GPSC firmware.
0 CLEAR INTO: This 80Cl 86 Microprocessor interrupt is set by an access of the GPSC
ID /Vector register (except on an interrupt acknowledge cycle). Bit O is cleared during the
interrupt service routine by an access of the 80CI86 Microprocessor address Ox 0488. Bit O is
undefined on powerup and is cleared by the firmware.
FUNCTIONAL DESCRIPTION 3-195