AT&T 3B2/300 Technical Reference Manual page 423

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
Peripheral Control and Status Register
The NI card contains an 8-bit Peripheral Control and Status Register (PCSR) which is addressable
on the lower data byte of the I/0 address (Ox 048F-Ox 0488). Each address corresponds to a single bit
of the PCSR. These bits are reset by an 80186 Microprocessor read or write access.
NI PERIPHERAL CONTROL AND STATUS REGISTER
BIT
DESCRIPTION
7
REQUEST SYSTEM BOARD CPU INTERRUPT: PCSR7[0] maps to the I/0 bus signal
PINTl[O] and is asserted by the NI firmware. When negated [1] by hardware, the interrupt has
been acknowledged by the system board CPU. When asserted [OJ, the interrupt request is
pending. A system reset negates the bit to a logic 1 (interrupt acknowledged). Addressing
PCSR7[1] (Ox 048F) clears (negates) the bit.
6
1/0 BUS LOCKED: This bit is used for the BAF. Bit 6 is set [1] by hardware when the 80186
Microprocessor is delayed in accessing main memory and must be cleared by firmware.
During normal operation, PCSR6 is cleared by the 80186 Microprocessor addressing PCSR6
unless a "dummy" read is pending. The 80186 Microprocessor cannot access DPDRAM when
PCSR6 is set [1 ]. Addressing PCSR6 (Ox 048E) clears (negates) the bit.
5
Used to control Asynchronous Data Ready (ARDY[l ]). Addressing PCSRS asserts ELPBK[O]
signal.
4
PCSR4 is reserved for future NI development. Addressing PCS4[1] (Ox 48C) clears (negates)
the bit.
3 PCSR3 is not used by the NI card. Addressing PCSR3 (Ox 0486) clears (resets) the bit.
2 PCSR2 is not used by the NI card. Add:essing PCSR3 (Ox 048A) clears (resets) the bit.
1
CLEAR INTI: This 80186 Microprocessor interrupt is set by a system board CPU access of the
NI PCSR (attention interrupt). PCSRl is cleared during the interrupt service routine by an
access of the 80186 Microprocessor address Ox 0489. Following a system reset the state of
PCSRl is undefined and is cleared by the NI firmware.
0
CLEAR INTO: This 80186 Microprocessor interrupt is set by a system board CPU access of the
NI ID/Vector Register (except on an interrupt acknowledge cycle). This interrupt is the
SYSGEN and Express Queue interrupt. Bit O is cleared during the interrupt service routine by
an access of the 80186 Microprocessor address Ox 0488. Bit O is undefined on powerup and is
cleared by the NI firmware.
3-170 TECHNICAL REFERENCE MANUAL