AT&T 3B2/300 Technical Reference Manual page 421

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
MEMORY
1/0
ADDRESS ADDRESS
Ox 00000
-
Ox 00080 -
Ox 00180 -
Ox 20000 -
Ox 40000 -
Ox 80000
-
Ox AOOOO
-
Ox COOOO Ox 0400
Ox C0080 Ox 0480
Ox C0082 Ox 0482
Ox C0082 Ox 0484
Ox C0086 Ox 0486
Ox C0088 Ox 0488
Ox C0089 Ox 0489
Ox COOSA Ox 048A
Ox COOSB Ox 048B
Ox COOSC Ox 048C
Ox COOSD Ox 0480
Ox COOSE Ox 048E
Ox C008F Ox 048F
Ox COlOO Ox 0500
Ox C0180 Ox 0580
Ox C0200
Ox 0600
Ox C0280 Ox 0680
Ox C0300 Ox 0700
Ox C0400 Ox FFOO
Ox C0420 Ox FF20
Ox C0450 Ox FFSO
Ox C0458 Ox FF58
Ox C0460 Ox FF60
Ox C04AO Ox FFAO
Ox C04CO Ox FFCO
Ox C04DO Ox FFDO
Ox C04FE Ox FFFE
Ox FOOOO
-
(NOTE 4)
-
NOTES:
LEGEND:
NI CARD ADDRESS MAP
CHIP
DESCRIPTION ACCESS
SELECT
LCS RAM (VECTOR TABLE) READ/WRITE
LCS RAM(DEMON) READ/WRITE
LCS RAM (USER) READ/WRITE
LCS UNUSED
-
(NOTE 1) UNUSED -
MCS DPDRAM READ/WRITE
MCS NOT USED -
PSO DEMON -
PSl ID/VECTOR REGISTER WRITE
PSl PAGE REGISTER WRITE
PSl PCSR BITS 7-0 READ
PSl RESERVED
PSl PCSR BIT O (INTO)
(NOTE 2)
PSl PCSR BIT 1 (INTl) (NOTE 2)
PSl PCSR BIT 2 (INT2) (NOTE 2)
PSl PCSR BIT 3 (INT3)
(NOTE 2)
PSl PCSR BIT 4 (NOT USED) (NOTE 3)
PSl PCSR BIT 5 (ARDY)
(NOTE 3)
PSl PCSR BIT 6 (BAF) (NOTE 3)
PSl PCSR BIT 7 (PINTl[O]) (NOTE 2)
PS2 NOT USED -
PS3 NOT USED -
PS4 DUART O AND 1
-
PSS DUART 2 AND 3 -
PS6 PARALLEL PORT -
80186 80186 CONTROL BLOCK -
80186 INTERRUPT CONTROL
-
80186 TIMER O CONTROL -
80186 TIMER 1 CONTROL
-
80186 TIMER 2 CONTROL
-
80186 CHIP SELECT CONTROL -
80186 OMA O CONTROL -
80186 OMA 1 CONTROL
-
80186 RELOCATION REGISTER -
ucs
ROM READ
ucs
DEMON ROM READ
1. External address decoding is required to select addresses
in the Ox 40000 - Ox 7FFFF range.
2. Bit is cleared [OJ (reset) by 80186 Microprocessor access.
3. Bit is cleared [OJ (reset) by 80186 Microprocessor access
unless "dummy" read of BAF is pending.
WIDTH
(BITS)
16
16
16
-
-
16
-
-
16
7
8
1
1
1
1
1
1
1
1
-
-
-
-
-
16
16
16
16
16
16
16
16
16
16
16
4. The application links ROM firmware with a DEMON function that
is limited to 128 bytes.
ARDY
BAF
OMA
DPDRAM
LCS
MCS
NRZI
PCSR
PS
ucs
Asynchronous Data Ready
Bus Abort Feature
Direct Memory Access
Dual Port Dynamic Random Access Memory
Lower RAM Chip Select
Memory Chip Select
Nonretum to Zero Insertion
Peripheral Control and Status Register
Peripheral Select
Upper RAM Chip Select
Figure 3-54: CMl 95A NI Card Address Map
3-168 TECHNICAL REFERENCE MANUAL
SIZE
(BYTES)
128
256
255.6K
128K
256K
128K/PAGE
128K
128
2
1
1
-
-
-
-
-
-
-
-
128
128
128
128
128
256
32
8
8
6
10
12
12
2
63.9K
128