AT&T 3B2/300 Technical Reference Manual page 319

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
Read Only Memory
The Read Only Memory (ROM) is equipped as either a 32K byte or a 64K byte ROM. Systems
equipped with the DEbug MONitor (DEMON) firmware use the 64K byte ROM. Four 16K by 8 read
only memory integrated circuits (27128's) form a 64K byte ROM. Four 8K by 8 read only memory
integrated circuits (2764's) form a 32K byte ROM. The starting address of ROM is Ox 00000000.
Timers
The timers include the following:
• Time of day (MM58174)
• Periodic (INTEL 8253)
• Sanity (INTEL 8253)
• Bus (INTEL 8253).
The periodic, sanity, and bus timers are an INTEL 8253 Programmable Interval Timer (PIT)
package. The PIT package contains three independent 16-bit counters.
Clock/Calendar Timer.
The Clock/Calendar Timer (MM58174) calculates current date to tenths of
a second. The timer is controlled by a 32.768-kHz oscillator. The timer features automatic leap year
calculation, protection for read access when changing data, and low standby current (2.2 volt, 10
microamperes). The accuracy is determined by the 32.768-kHz crystal with a 0.003 percent tolerance
( ±
1.3 minutes per month).
Periodic Timer. The Periodic Timer (Timer 1) is a self-restarting count down timer. The time base
is 100 kHz (CLKTA[l ]). Each time Timer 1 reaches zero, the Periodic Interrupt bit (bit 6) is set in the
CSR and a level 15 interrupt is sent to the Interrupt Decoder. The Periodic Interrupt is latched in the
CSR and the level 15 interrupt asserted until CSR bit 6 is cleared by writing to address Ox 00042010.
Sanity Timer.
The Sanity Timer (Timer 0) is a count down timer that is normally reset by software
before it reaches zero. The time base is 100 kHz (CLKTB[l ]). When the Sanity Timer reaches zero, an
error signal turns on the Diagnostic indicator, a level 15 interrupt is sent to the Interrupt Decoder, and
the Error Timer Time-out bit (bit 15) is set in the CSR. The CSR bit 15 is cleared by writing to address
Ox 00044000. This count down timer is started when the power switch is pressed to OFF. System
software must read the 8253 package to determine whether Sanity Timer (Timer 0) or the Bus Timer
(Timer 2) timed out.
Bus Timer.
The Bus Timer (Timer 2) is a count down timer that controls time-outs on the address
bus. The time base is 2 MHz (CLK02[1 ]). Timer 2 is used to generate a fault for addresses that do not
respond (send an acknowledge signal). The Bus Timer is reset when the arbiter's acknowledge is
inactive. When the Bus Timer reaches zero, a bus time-out signal is sent to the DRAM and Arbiter
Circuits, an error signal turns on the Diagnostic indicator, a level 15 interrupt is sent to the Interrupt
Decoder, and the Error Timer Time-out bit (bit 15) is set in the CSR. The CSR bit 15 is cleared by
writing to address Ox 00044000. System software must read the 8253 package to determine whether
Sanity Timer (Timer 0) or the Bus Timer (Timer 2) timed out.
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