AT&T 3B2/300 Technical Reference Manual page 276

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Peripheral Controller Main Memory Write Operation.
Figure 3-9 shows the peripheral controller
main memory write operation. A main memory write by a peripheral controller (feature card) starts
with the feature card asserting an I/0 bus access request (PBRQ[O]). When the feature card receives the
Peripheral Bus Acknowledge (PBACK[O]), the feature card asserts the Peripheral Bus Busy (PBUSY[O])
signal. The feature card gates the following signals onto the I/0 bus to start the data transfer:
• Physical Address (P A23-00[1])
• Peripheral Read/Write (PR[l ]W[O]) (0 for write operation)
• Peripheral Size (PSIZE16[0]).
When the address and control signals are stable, the Peripheral Physical Address Strobe (PP AS[O])
and Peripheral Data Strobes (PDSl-0[0]) are asserted. The PBRQ is negated after the data transfer
operation has started (following assertion of the PP AS and negation of PBACK). The peripheral
controller gates the write data onto the I/0 bus Peripheral Data lines (PDlS-00[1 ]). When the data is
stable, the peripheral controller asserts the appropriate Peripheral Data Strobe(s). Then, the main
memory latches the data and asserts the Peripheral Data Acknowledge (PDT ACK[O]) signal. The
feature card negates the strobes and bus busy signals and then tri-states the I/0 bus. The main
memory control negates the PDT ACK signal when the data strobes are removed.
FUNCTIONAL DESCRIPTION 3-23