AT&T 3B2/300 Technical Reference Manual page 338

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
CM518A/B/C System Boards
Figure 3-27 is a functional block diagram of the Version 3 system board. The Version 3
382 computer system board features are listed below:
• Central Processing Unit (CPU)
• Memory Management Unit (MMU) (two MMUs on CM518C)
• Math Acceleration Unit (MAU)
• Time-of-Day (TOD), interval, system sanity, and unbuffered bus timers
• 32-bit Control, Status, and Error Register (CSER)
• Nine interrupt levels including nonmaskable interrupts
• Two RS-232C serial ports with data set control
• Floppy controller with digital data separator (no adjustments)
• Direct Memory Access Controller (DMAC) for integral floppy disk and Universal Asynchronous
Receiver/Transmitters (UARTs)
• 2 megabytes to 64 megabytes of Dynamic Random Access Memory (DRAM) with hardware
refresh and Error Correction Code (ECC)
• Supports 8- and 16-bit feature cards
• Power reset of system board and feature cards
• "Soft power" control
• 2K by 8-bit Nonvolatile Random Access Memory (NVRAM)
• 3.6 volt DC lithium battery for NVRAM, TOD clock, and feature cards
• Synchronous memory controller up to 24 MHz
• Supports a 12-slot Enhanced Input/Output (EIO) bus with sequential access capability
• Supports both buffered and unbuffered microbus slots.
Functionally, the CM518 System Boards are very similar. Physically, the CM518A uses a WE 32100
chipset while the CM518B/C System Boards use the WE 32200 chipset. The CM518C System Board
also has two MMUs (WE 32201). Refer to Chapter 2, Equipment Description, for information on the
physical configuration of the CM518 System Boards.
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