AT&T 3B2/300 Technical Reference Manual page 481

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - - -
Peripheral Control and Status Register
The ISC card contains an 8-bit Peripheral Control and Status Register (PCSR) which is addressable
on the lower data byte of the 1/0 address (Ox 048F-Ox 0488). Each address corresponds to a single bit
of the PCSR. These bits are reset by an 80186 Microprocessor read or write access except for PCSR6
that is controlled by the BAF.
ISC PERIPHERAL CONTROL AND ST A TUS REGISTER
BIT DESCRIPTION
7 REQUEST SYSTEM BOARD CPU INTERRUPT: PCSR7[0] maps to the 1/0 bus signal
PINTl[O] and is asserted by the !SC firmware. When negated [1] by hardware, the interrupt
has been acknowledged by the system board CPU. When asserted [OJ, the interrupt request is
pending. A system reset negates the bit to a logic 1 (interrupt acknowledged). Addressing
PCSR7[1] (Ox 048F) clears (negates) the bit.
6 1/0 BUS LOCKED: This bit is used for the BAF. Bit 6 is set by hardware when the 80186
Microprocessor is delayed in accessing main memory and must be cleared by firmware.
During normal operation, PCSR6 is cleared by the 80186 Microprocessor addressing PCSR6
unless a "dummy" read is pending. Addressing PCSR6 (Ox 048E) clears (negates) the bit.
5 Not used by the !SC card.
4
Not used by the !SC card.
3
CLEAR INT3: This 80186 Microprocessor interrupt is set by the 8237 OMA Controller. Bit 3
is cleared during the interrupt service routine by an access of the 80186 Microprocessor address
Ox 0488.
2
CLEAR INT2: This 80186 Microprocessor interrupt is set by the 8274 Dual Channel
Communications Chip. Bit 2 is cleared during the interrupt service routine by an access of the
80186 Microprocessor address Ox 048A.
1 CLEAR INTl: This 80186 Microprocessor interrupt is set by a system board CPU access of the
!SC PCSR (attention interrupt). PCSRl is cleared during the interrupt service routine by an
access of the 80186 Microprocessor address Ox 0489. Following a system reset the state of
PCSRl is undefined and is cleared by the !SC firmware.
0
CLEAR INTO: This 80186 Microprocessor interrupt is set by an access of the !SC ID/Vector
Register (except on an interrupt acknowledge cycle). Bit O is cleared during the interrupt
service routine by an access of the 80186 Microprocessor address Ox 0488. Bit O is undefined
on powerup and is cleared by the firmware.
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