AT&T 3B2/300 Technical Reference Manual page 498

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CM195W PERIPHERAL CONTROL AND STATUS REGISTER (Contd)
BIT DESCRIPTION
07
REQUEST SYSTEM BOARD CPU INTERRUPT: PCSR07[0] maps to the 1/0 bus signal
PINTO[OJ and is asserted by the CMl 95W firmware. When negated [1] by hardware, the
interrupt has been acknowledged by the system board CPU. When asserted [OJ, the interrupt
request is pending. A system reset negates the bit to a logic 1 (interrupt acknowledged).
Addressing PCSR7[1 J (Ox 048F) clears (negates) the bit.
06
INT2-SCSI PROTOCOL CONTROLLER CHIP (SPCC) INTERRUPT: PCSR06[0] is used to
indicate the current state of the NCR 5386 SPCC interrupt request. PCSR06 is cleared by
reading the 5386 Interrupt Request Register. Addressing PCSR6 (Ox 0400) clears (negates) the
bit.
05
NONMASKABLE INTERRUPT: PCSR05[0] is used to indicate the CMl 95W received a
peripheral fault during a OMA transfer between the FIFO and main memory. Addressing
PCSR05 (Ox 0480) clears (negates) the bit. On powerup, PCSR05 is undefined and is cleared
by firmware.
04 INT3-8237 OMA COMPLETION INTERRUPT: PCSR04[0] is used to indicate an end of
process has been reached during a OMA transfer from the main memory to the FIFO. PCSR04
is set by the 8237 and is cleared by addressing PCSR04 (Ox 048C). On powerup, PCSR04 is
undefined and is cleared by firmware.
03
INT3-8237 OMA COMPLETION INTERRUPT: PCSR03[0] is used to indicate an end of
process has been reached during a OMA transfer from the main memory to the FIFO. PCSR04
is set by the 8237 and is cleared by addressing PCSR03 (Ox 0486). On powerup, PCSR03 is
undefined and is cleared by firmware.
02
INT2-SCSI BUS RESET: PCSR02[0] is set when a SCSI bus reset condition is detected.
Addressing PCSR02 (Ox 048A) clears the bit; however, the bit remains set as long as the SCSI
bus reset condition exists. On powerup, PCSR02 is undefined and is cleared by firmware.
01
INTl-SYSGEN ATTENTION INTERRUPT: PCSROl is set by a CPU system board access
of the CM195W Control Register. PCSROl is cleared during the interrupt service routine by an
access of the 80186 Microprocessor address Ox 0489. Following a system reset the state of
PCSRl is undefined and is cleared by the CMl 95W firmware.
00 INTO-PRE-SYSGEN/EXPRESS INTERRUPT: This 80186 Microprocessor interrupt is set by
an access of the CM195W ID/Vector Register (except on an interrupt acknowledge cycle). This
interrupt is the SYSGEN and Express Queue interrupt. PCSROO is cleared during the interrupt
service routine by an access of the 80186 Microprocessor address Ox 0488. Bit O is undefined
on powerup and is cleared by the firmware.
FUNCTIONAL DESCRIPTION 3-245