AT&T 3B2/300 Technical Reference Manual page 512

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CM521A PERIPHERAL CONTROL AND ST A TUS REGISTER (Contd)
BIT DESCRIPTION
07
REQUEST SYSTEM BOARD CPU INTERRUPT: PCSR07[0] maps to the 1/0 bus signal
PINTO[O] and is asserted by the CM52IA firmware. When negated [1] by hardware, the
interrupt has been acknowledged by the system board CPU. When asserted [OJ, the interrupt
request is pending. A system reset negates the bit to a logic 1 (interrupt acknowledged).
Addressing PCSR7[1] (Ox 048F) clears (negates) the bit.
06
SPINTR[l]-SCSI PROTOCOL CONTROLLER CHIP (SPCC) INTERRUPT: PCSR06[0] is
used to indicate the current state of the MB87030 SPCC interrupt request. PCSR06 is cleared
by reading the 5386 Interrupt Request Register. Addressing PCSR6 (Ox 040D) clears (negates)
the bit.
05
NONMASKABLE INTERRUPT: PCSR05[0] is used to indicate the CM52IA received a
peripheral fault during a DMA transfer between the FIFO and main memory. Addressing
PCSR05 (Ox 048D) clears (negates) the bit. On powerup, PCSR05 is undefined and is cleared
by firmware.
04 82C37 DMA COMPLETION INTERRUPT: PCSR04[0] is used to indicate an end of process
has been reached during a DMA transfer from the FIFO to the main memory. PCSR04 is set
by the 82C37 and is cleared by addressing PCSR04 (Ox 048C). On powerup, PCSR04 is
undefined and is cleared by firmware.
03 CINT3-82C37 DMA COMPLETION INTERRUPT: PCSR03[0] is used to indicate an end of
process has been reached during a DMA transfer from the main memory to the FIFO. PCSR04
is set by the 82C37 and is cleared by addressing PCSR03 (Ox 048B). On powerup, PCSR03 is
undefined and is cleared by firmware.
02
PSSSAO-SYSTEM BOARD SUPPORTS SEQUENTIAL ACCESS: PCSR02[0] is set when
the system board supports sequential access data transfers. Addressing PCSR02 (Ox 048A)
clears the bit. On powerup, PCSR02 is undefined and is cleared by firmware.
01 CINTl-SYSGEN ATTENTION INTERRUPT: PCSROl is set by a CPU system board access
of the CM52IA Control Register. PCSROl is cleared during the interrupt service routine by an
access of the 80CI86 Microprocessor address Ox 0489. Following a system reset the state of
PCSRl is undefined and is cleared by the CM52IA firmware.
00
CINTO-PRE-SYSGEN/EXPRESS INTERRUPT: This 80CI86 Microprocessor interrupt is set
by an access of the CM52IA ID /Vector Register (except on an interrupt acknowledge cycle).
This interrupt is the SYSGEN and Express Queue interrupt. PCSROO is cleared during the
interrupt service routine by an access of the 80CI86 Microprocessor address Ox 0488. Bit O is
undefined on powerup and is cleared by the firmware.
FUNCTIONAL DESCRIPTION 3-259