AT&T 3B2/300 Technical Reference Manual page 303

FUNCTIONAL D E S C R I P T I O N - - - - - - - - - - - - - - - - - - - - - - - - - -
Peripheral Mode. In the peripheral mode of MMU operation, the MMU is accessed as a
memory-mapped peripheral. In this mode, internal MMU registers and logic elements are read and
write accessible by the system board CPU. All peripheral mode accesses are word (32-bit) accesses.
When the system board CPU asserts the MMU Chip Select (MMUCS[O]), the MMU is in the peripheral
mode. The internal MMU address spectrum is shown in Figure 3-17. In the peripheral mode, physical
address bits 31-00 are interpreted as follows by the MMU.
PERIPHERAL MODE ADDRESS FIELDS
BITS 31- 12 11- 08 07 06 - 02 01 - 00
FIELD RESERVED ENTITY RESERVED INDEX RESERVED
The peripheral mode address fields are defined in the following paragraphs.
RESERVED
ENTITY
INDEX
Bits 31-12, 07, 01, and 00 are ignored by the MMU. These bits are negated
(treated as zeros).
Bits 11-08 are used to select the internal MMU circuit (entity) to be accessed. The
decode of bits 11-08 is as follows.
BITS 11 - 08 SELECTED MMU DEVICE
0000 SEGMENT DESCRIPTOR CACHE BITS 31-00
0001 SEGMENT DESCRIPTOR CACHE BITS 63-32
0010 RIGHT HALF OF PAGE DESCRIPTOR CACHE BITS 31-00
0011 RIGHT HALF OF PAGE DESCRIPTOR CACHE BITS 63-32
0100 LEFT HALF OF PAGE DESCRIPTOR CACHE BITS 31-00
0101 LEFT HALF OF PAGE DESCRIPTOR CACHE BITS 63-32
0110 SECTION RAM A
0111 SECTION RAM B
1000 FAULT CODE REGISTER
1001 FAULT ADDRESS REGISTER
1010
CONFIGURATION REGISTER
1011
VIRTUAL ADDRESS REGISTER
Bits 06-02 are used to index each addressable entity. Bits 06-02 are ignored
when registers are accessed. Bits 06-02 are used when segment or page descriptor
caches are accessed. Bits 03 and 02 are used for section RAM accesses.
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