AT&T 3B2/300 Technical Reference Manual page 354

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FAULT TYPE
Bits 04-00 are the FAULT TYPE that occurred. The decode of bits 04-00 indicate
the following. Unassigned fault type values are not included.
BITS 04-00 FAULT NAME
00000 NO FAULT
00001 MISPROCESSING MEMORY
00010 REFERENCED/MODIFIED UPDATE MEMORY
00011 SEGMENT DESCRIPTOR TABLE LENGTH
00100 PAGE WRITE
00101 PAGE DESCRIPTOR TABLE LENGTH
00110 INV AUD SEGMENT DESCRIPTOR
00111 SEGMENT NOT PRESENT
01000 RESERVED
01001
PAGE DESCRIPTOR TABLE NOT PRESENT
01010 PAGE NOT PRESENT
01011 TOO MANY INDIRECTIONS
01101 ACCESS
01110
ACCESS OFFSET
01111 RESERVED
Fault Address Register
The Fault Address Register (FLTAR) contains the virtual address that was being processed when the
last fault that caused a write to the FLTCR occurred. The output of the /etc/errdump command
includes the FLT AR.
Virtual Address Register
The Virtual Address Register (VAR) contains the virtual address to be translated by the MMU. The
VAR is overwritten each time a translation is performed. Writing to the VAR causes the corresponding
page descriptor and segment descriptor to be flushed. If the segment descriptor is contiguous, then all
page descriptors are flushed.
Configuration Register
The Configuration Register (CR) is used to enable or disable certain options of the MMU. Upon
reset, all bits are cleared. The format of the CR is as follows.
CONFIGURATION REGISTER
BITS 31- 07 06 05 04 - 03 02 01
00
FIELD RESERVED DCE MCE PS CACHEABLE REFERENCED MODIFIED
The CR fields are defined in the following paragraphs.
RESERVED
DCE
MCE
Bits 31-07 are reserved for future use. If read, zeros are returned.
Bit 06 is the Data Cache Enable (DCE) bit. This bit must be set to enable data
cache. For parts without data cache, this bit must contain a zero.
Bit 05 is the Multiple Context Enable (MCE) bit. When set (1 ], the multiple context
feature is enabled. When cleared[O], the MMU operates is single context mode.
FUNCTIONAL DESCRIPTION 3-101