AT&T 3B2/300 Technical Reference Manual page 430

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
1/0 Bus Interface
The only operation supported by the AIC hardware is a "read" by the integral CPU. A read
operation at a specific address will cause a specific result. The addresses and corresponding results are
shown in Figure 3-56.
CSR
OFFSET LIMIT
BIT
RESULT
OXOO OXOl - READ BOARD ID (ID=Ox0101)
OX04 OX05
-
READ 16 BIT AIC STATUS REGISTER
OX20 - 00 SET SWMJNORl TO CAUSE MINOR ALARM FROM SOFTWARE
OX21
-
00 CLEAR SWMINORl
OX22
-
01 SET SWMAJORl TO CAUSE MAJOR ALARM FROM SOFTWARE
OX23 - 01 CLEAR SWMAJORl
OX24 - 02 SET SANENl TO ENABLE SANITY TIMER
OX25 - 02 CLEAR SANENl TO DISABLE SANITY TIMER
OX26
-
03 NO FUNCTION
OX27 -
03
CLEAR SANITY TIMER (PRESENTS A LOGIC 0
ON STATUS REGISTER BIT 03 FOR 127.5 MILLISECONDS)
OX28 - 04 SET INHALRMl TO INHIBIT ALL ALARMS
OX29
-
04 CLEAR INHALRMl TO ENABLE ALARMS
OX2A
-
05
SET ACFAILl FOR DIAGNOSTIC TEST OF THIS BIT
OX2B - 05 CLEAR ACFAILl TO CLEAR THIS BIT FROM CSR
OX2C - 06 SET LOWBATl FOR DIAGNOSTIC TEST OF THIS BIT
OX2D
-
06 CLEAR LOWBATl (CLEARS LOW BATTERY STATUS FROM CSR)
OX2E - 07 SET EXTTL21 FOR DIAGNOSTIC TEST OF THIS BIT
OX2F - 07 CLEAR EXTTL21 (CLEARS EXTERNAL MAJOR ALARM FROM CSR)
OX30
-
08 SET EXTTLl 1 FOR DIAGNOSTIC TEST OF THIS BIT
OX31 - 08 CLEAR EXTTLll (CLEARS EXTERNAL MINOR ALARM FROM CSR)
OX32
-
09 SET ISANEl BIT 9 FOR DIAGNOSTIC TEST OF THIS BIT
OX33
-
09 CLEAR INSANE! INDICATION OF SANITY TIMEOUT FROM CSR
OX34 - 10 SET BIT 10 TO SET TMOUTl TO 1 AND ASSERT PINT20
OX35
-
10 CLEAR BIT 10 TO CLEAR TMOUTl ONLY
OX36
- -
CLEAR PENDING PINT20
OX37
-
-
CAUSE SYSTEM RESET VIA 1/0 BUS LEAD RQRSTO
OX38
-
12
RESERVED
OX39
-
12 RESERVED
OX3A
-
13 RESERVED
OX3B
-
13
RESERVED
OX3C
-
14 RESERVED
OX3D
-
14 RESERVED
OX3E
-
15 TRMl AND TRM2 DTRT IS CONTROLLED BY 3B2 UART
OX3F - 15 TRMl AND TRM2 DTR IS FORCED ACTIVE
(POWER UP DEFAULT STATE)
Figure 3-56: CM195AA AIC Card Address Spectrum
FUNCTIONAL DESCRIPTION 3-177