AT&T 3B2/300 Technical Reference Manual page 344

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Bus Interface Control.
The bus interface control provides all strobes and control signals necessary
to interface with peripherals.
Main Controller.
The main controller is responsible for acquiring and decoding instruction opcodes
and directing the action of the fetch and execute controllers as the specified instruction is executed. The
main controller also responds to and directs the handling of interrupts and exceptions.
Fetch Unit.
The fetch unit handles the instruction stream and does memory-based operand
accesses. The unit consists of a fetch controller, an instruction cache, and instruction queue, an
immediate and displacement extractor, and an Address Arithmetic Unit (AAU).
Execute Unit.
The execute unit does all arithmetic, binary coded decimal, logical operations, all
shift and rotate operations, and computes condition flags. It consists of an execute controller, thirty-two
32-bit registers, working registers, and a 33-bit wide Arithmetic Logic Unit (ALU). The thirty-two
32-bit registers are user-accessible. These registers include 17 general-purpose registers (r23-rl6, r8-
r0), 8 general-purpose kernel registers (r31-r24), and 7 dedicated registers (r15-r9). All registers
except the program counter (r15) and the process status word (rl 1) can be referenced in all addressing
modes. The general-purpose kernel registers (r31-r24), processor status word (rll), process control
block pointer (r13), and the interrupt stack pointer (r14) are privileged registers that can be read at any
time, but these registers can only be written when the CPU is in the kernel (highest) execution level.
The working registers are used exclusively by the CPU and are not user-accessible. The thirty-two
32-bit CPU registers are further defined in the following paragraphs.
FUNCTIONAL DESCRIPTION 3-91