AT&T 3B2/300 Technical Reference Manual page 376

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Interrupts
Interrupt Mechanism.
When an external device requests an interrupt (request for service to the
microprocessor), the microprocessor temporarily stops its current execution and begins executing code
that services the interrupt. This code is called an interrupt handler. On completion of the interrupt
handler code, execution resumes at the point where the interrupt occurred. An interrupt mechanism
performs the process execution switch.
There are three functions of the interrupt mechanism, as follows.
1. The interrupt mechanism determines whether or not there will be an interrupt generated in
response to an interrupt request. An interrupt is generated if the priority level requested is
greater than the priority level in the Interrupt Priority Level (IPL) field of the Processor Status
Word (PSW) register of the CPU. If the IPL field equals Ox F, no interrupts are acknowledged
except for a nonmaskable interrupt.
2. The interrupt mechanism determines how an interrupt request will be acknowledged and the
interrupt identification value. Interrupts are acknowledged as full or quick interrupts. A full
interrupt starts an interrupt-handler process by means of a full context/process switch. A quick
interrupt causes the interrupt handler to store the current Program Counter (PC) register and
PSW register values on the execution stack and set the IPL field of the PSW to Ox F (like a
subroutine call). Only a nonmaskable interrupt can interrupt the quick-interrupt handler. A
nonmaskable interrupt causes the interrupt handler to store the current PC and PSW values on
the execution stack just like a quick interrupt. An interrupted interrupt handler's execution is
resumed as a function of popping saved states off the execution stack.
3. The interrupt mechanism saves the interrupted process context and brings in a new process
context (process switching). Interrupt-vector tables are provided for full and quick interrupts.
The interrupt-vector tables point to the memory locations (addresses) where interrupt PCBPs and
PC/PSW pairs are stored.
Interrupt Logic.
Eight hardware interrupts are provided. Three of these levels (PINT2-0(0]) are
connected to the Input/Output Expansion connector for use by the feature cards that supply their own
interrupt vectors. Two interrupt levels are used as Programmed Interrupt Requests (PIRs) and are
accessible via the Control, Status, and Error Register (CSER). The three remaining interrupt levels are
used by the system board for peripheral devices.
To acknowledge three off-board requests, the interrupt hardware requests the DRAM controller to
enter the "bypass" mode. When the controller responds with a "bypass mode" acknowledge, the
interrupt acknowledge cycle proceeds and the vector is read from the interrupting off-board device.
Interrupt levels are encoded by an 8 /3 encoder and applied to the CPU interrupt request inputs as
level 15 through 8 interrupts. When interrupts are acknowledged, the CPU uses the address bus bits 05
through 02 to identify the acknowledged level. In the virtual mode (V AD(O]=O), a latched version of
address bits 05 through 02 are used by the interrupt circuitry. When bit 2 is low and either bit 3 or
bit 4 is high, an off-board interrupt is assumed and an arbiter request is made. When the bus arbiter
permits access, the proper off-board interrupt acknowledge signal is sent. Other combinations of
address bits 05 through 02 are assumed to be onboard interrupts and a vector is supplied by looping
the latched address bits 05 through 02 back to the data bus via a buffer. A unique vector is provided
for each onboard interrupt source that is equal to the interrupt level. When an onboard interrupt is
decoded, the interrupt circuit sends a wait select (WSELl[O]).
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