AT&T 3B2/300 Technical Reference Manual page 266

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Intelligent Controllers. Intelligent controllers are feature cards containing one or more
microprocessors that are capable of autonomously executing programs stored on the cards. The use of
intelligent feature cards is a major factor in achieving the high performance capabilities of a
3B2 computer. Intelligent feature cards use request and completion queues to communicate with the
system board CPU. Most of the 3B2 computer feature cards are intelligent controllers. The Common
Input/Output (CIO) architecture of intelligent controllers includes the following:
• Central Processing Unit (CPU)
• Input/Output (1/0) Bus Control
• Identification/Vector (ID /Vector) Register
• Page Register
• Peripheral Control and Status Register (PCSR)
• Onboard Random Access Memory (RAM)
• Onboard Read Only Memory (ROM)
• Miscellaneous Support Logic.
Bus Abort Feature.
The Bus Abort Feature (BAF) is a defensive measure against the loss of data
from a serial port. Since memory is a shared resource, the peripheral controller can be prevented from
rapidly accessing the 1/0 bus. When a peripheral controller can not rapidly access the I/0 bus, serial
port data can be lost. To prevent this, intelligent controllers can abort the bus request cycle and resume
autonomous processing.
Intelligent controllers use an INTEL 80186 Microprocessor. Timer 1 of the 80186 Microprocessor is
used as a bus timer. This timer is reset at the start of each bus cycle. If a bus access cycle fails to
complete within the programmed interval, the timer forces a ready condition to the 80186
Microprocessor. This sets the Peripheral Control and Status Register bit 6 (internal timer interrupt).
The 80186 Microprocessor bus cycle is aborted by the bus time-out; however, the bus request is still
active. Therefore, the I/0 bus cycle continues after the bus time-out until a bus acknowledge is
received. Following the bus time-out, the 80186 Microprocessor does not use the I/0 bus until the
"dummy" read cycle is complete. The "dummy" read cycle is executed in response to the bus
acknowledge for the pending bus request.
FUNCTIONAL DESCRIPTION 3-13