AT&T 3B2/300 Technical Reference Manual page 404

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Memory Control Signals
The memory control signals include the following:
BANKEN(3-0)[0]
CAS3-0[0]
CE(3-0)[0]
RAS[O]
RE(3-0)[0]
WE(3-0)[0]
The "bank enable" signals are used to select (enable) the read or write access of
individual memory array banks.
The "column address strobes" signals are used to strobe (enable) the column
address.
The "CAS enable" signals are buffered versions of CAS(3-0)(0] and are used to
enable the column address into the memory chips of the designated bank (3-0).
The "row address strobe" signals are used to strobe (enable) the row address.
The "RAS enable" signals are buffered versions of RAS(O] and are used to enable
the row address into the memory chips of the designated bank.
The "write enable" signals are used to write data to the memory.
Note:
The enable signals operate on half-words, designated by "H" and "L" for "high order"
or "low order."
Memory Address Signals
Memory address signals are supplied from the Address Generation logic of the Dynamic Random
Access Memory Controller (DRAMC) via a 10-bit multiplexed memory address bus. Control signals
applied to the memory cards determine whether the address is used as a row or column address. The
relationship between the buffered microbus and the multiplexed memory address bus for row and
column addresses is shown in the following table. Note that all multiplexed address bus bits are NOT
necessarily used by a given RAM card.
BUFFERED MICROBUS MULTIPLEXED
ADDRESS
MEMORY
ADDRESS
ROW
COLUMN BUS
ADDRESS ADDRESS
BITS
BITS BITS
23 22
10
21 20 9
19
10
8
18
09
7
17 08
6
16
07 5
15 06 4
14 05 3
13
04
2
12 03 1
11 02
0
FUNCTIONAL DESCRIPTION 3-151