AT&T 3B2/300 Technical Reference Manual page 440

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Control Lines
The processing unit uses 28 control signals. They can be subgrouped as bus control, external chip
selects, and externally generated interrupts. Bus control signals may come from the INTEL 80186
Microprocessor, the external interface, or both. The following table shows the control lines and their
purpose.
SIGNAL GROUP
PURPOSE
PIHOLDl Bus Asserted to request the 80186 relinquish the bus
(external).
PIDRQll Bus
Request a OMA cycle from OMA Channel 1 (external).
PIURDYl Bus External device has transferred data (external).
PITESTl Bus Suspends execution of a wait instruction (external).
BRDPRESO Bus
When LOW, indicates an external board is present
(external).
PIHLDAl Bus Indicates the 80186 has yielded the bus.
PILOCKO Bus
Used to acquire sole control of a resource on a multibus.
PICLKOUTl Bus
8-MHz system clock.
PIRSTl Bus Reset from CPU.
PIIS[0-2]0 Bus Indicates bus cycle type.
PIRAMACKO Bus RAM has completed a cycle.
PIALEl Bus Address latch enable (valid on address leads).
PIWRO Bus Data valid for a write operation.
PIRDO Bus Data being strobed for a read operation.
PIBHEO Bus Used to indicate a word/byte transfer in conjunction
with PIADROOl.
PIDTlRO Bus Indicates data flow direction.
PIDENO Bus Indicates that data may be placed on the bus.
PIPCS[2-5]0 Chip
1/0 chip select lines.
Select
PIMCS[23]0 Chip Memory chip selects.
Select
PINMil External Used by an external board to generate a nonmaskable
Interrupt interrupt.
PIINTRAl External
Used by an external board to raise maskable interrupt 2
Interrupt on the 80186.
PIINTRBl External Used by an external board to raise maskable interrupt 3
Interrupt on the 80186.
Timer Input/Output
There are four timer inputs/outputs used to provide timer/counter capabilities to an external board.
Two timer inputs (PITMRINO and PITMRINl) and two timer outputs (PITMROO and PITMRlO) are
available and connected to timers O and 1 on the 80186 Microprocessor.
FUNCTIONAL DESCRIPTION 3-187